fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-06-11 20:38:32 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

brw: Assert that urb_vec4_intel stores only have 4/8 components

Browse source 
vec1-3, 5-7, and 9+ are not supported.  Only vec4 and vec8.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39250>
This commit is contained in:
Kenneth Graunke 2026-01-16 14:31:24 -08:00 • committed by Marge Bot
parent b844082017
commit dbb24ff56b
1 changed files with 2 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/intel/compiler/brw/brw_from_nir.cpp
View file

@ -5043,6 +5043,8 @@ brw_from_nir_emit_intrinsic(nir_to_brw_state &ntb,
brw_urb_inst *urb = bld.URB_WRITE(srcs, ARRAY_SIZE(srcs));
urb->components = instr->src[0].ssa->num_components;
urb->offset = urb_global_offset;
assert(urb->components == 4 || urb->components == 8);
break;
}