From dbb24ff56bebefc919f68ebe0a6c60c5d9800dbf Mon Sep 17 00:00:00 2001
From: Kenneth Graunke <kenneth@whitecape.org>
Date: Fri, 16 Jan 2026 14:31:24 -0800
Subject: [PATCH] brw: Assert that urb_vec4_intel stores only have 4/8
 components

vec1-3, 5-7, and 9+ are not supported.  Only vec4 and vec8.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39250>
---
 src/intel/compiler/brw/brw_from_nir.cpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/intel/compiler/brw/brw_from_nir.cpp b/src/intel/compiler/brw/brw_from_nir.cpp
index 68229413495..d5cc1075ddc 100644
--- a/src/intel/compiler/brw/brw_from_nir.cpp
+++ b/src/intel/compiler/brw/brw_from_nir.cpp
@@ -5043,6 +5043,8 @@ brw_from_nir_emit_intrinsic(nir_to_brw_state &ntb,
       brw_urb_inst *urb = bld.URB_WRITE(srcs, ARRAY_SIZE(srcs));
       urb->components = instr->src[0].ssa->num_components;
       urb->offset = urb_global_offset;
+
+      assert(urb->components == 4 || urb->components == 8);
       break;
    }