fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-06 00:49:04 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radv: add more radeon_opt_set_xxx variants

Browse source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28983>
This commit is contained in:
Samuel Pitoiset 2024-05-08 16:23:26 +02:00 • committed by Marge Bot
parent d5af67ea2c
commit db597d274b
1 changed files with 50 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

50
src/amd/vulkan/radv_cs.h
View file

@ -207,6 +207,23 @@ radeon_set_privileged_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigne
} \
} while (0)
#define radeon_opt_set_context_reg2(cmdbuf, reg, reg_enum, v1, v2) \
do { \
struct radv_cmd_buffer *__cmdbuf = (cmdbuf); \
struct radv_tracked_regs *__tracked_regs = &__cmdbuf->tracked_regs; \
const uint32_t __v1 = (v1), __v2 = (v2); \
if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 1, 0x3) || \
__tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2) { \
radeon_set_context_reg_seq(cmdbuf->cs, reg, 2); \
radeon_emit(cmdbuf->cs, __v1); \
radeon_emit(cmdbuf->cs, __v2); \
BITSET_SET_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 1); \
__tracked_regs->reg_value[(reg_enum)] = __v1; \
__tracked_regs->reg_value[(reg_enum) + 1] = __v2; \
cmdbuf->state.context_roll_without_scissor_emitted = true; \
} \
} while (0)
#define radeon_opt_set_context_reg3(cmdbuf, reg, reg_enum, v1, v2, v3) \
do { \
struct radv_cmd_buffer *__cmdbuf = (cmdbuf); \
@ -227,6 +244,39 @@ radeon_set_privileged_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigne
} \
} while (0)
#define radeon_opt_set_context_reg4(cmdbuf, reg, reg_enum, v1, v2, v3, v4) \
do { \
struct radv_cmd_buffer *__cmdbuf = (cmdbuf); \
struct radv_tracked_regs *__tracked_regs = &__cmdbuf->tracked_regs; \
const uint32_t __v1 = (v1), __v2 = (v2), __v3 = (v3), __v4 = (v4); \
if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 3, 0xf) || \
__tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2 || \
__tracked_regs->reg_value[(reg_enum) + 2] != __v3 || __tracked_regs->reg_value[(reg_enum) + 3] != __v4) { \
radeon_set_context_reg_seq(cmdbuf->cs, reg, 4); \
radeon_emit(cmdbuf->cs, __v1); \
radeon_emit(cmdbuf->cs, __v2); \
radeon_emit(cmdbuf->cs, __v3); \
radeon_emit(cmdbuf->cs, __v4); \
BITSET_SET_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 3); \
__tracked_regs->reg_value[(reg_enum)] = __v1; \
__tracked_regs->reg_value[(reg_enum) + 1] = __v2; \
__tracked_regs->reg_value[(reg_enum) + 2] = __v3; \
__tracked_regs->reg_value[(reg_enum) + 3] = __v4; \
cmdbuf->state.context_roll_without_scissor_emitted = true; \
} \
} while (0)
#define radeon_opt_set_context_regn(cmdbuf, reg, values, saved_values, num) \
do { \
struct radv_cmd_buffer *__cmdbuf = (cmdbuf); \
if (memcmp(values, saved_values, sizeof(uint32_t) * (num))) { \
radeon_set_context_reg_seq(cmdbuf->cs, reg, num); \
radeon_emit_array(cmdbuf->cs, values, num); \
memcpy(saved_values, values, sizeof(uint32_t) * (num)); \
__cmdbuf->state.context_roll_without_scissor_emitted = true; \
} \
} while (0)
ALWAYS_INLINE static void
radv_cp_wait_mem(struct radeon_cmdbuf *cs, const enum radv_queue_family qf, const uint32_t op, const uint64_t va,
const uint32_t ref, const uint32_t mask)