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radv: add graphics shaders context registers that need to be tracked

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28983>
This commit is contained in:
Samuel Pitoiset 2024-05-08 16:23:22 +02:00 • committed by Marge Bot
parent 9532b0f1b2
commit d5af67ea2c
1 changed files with 48 additions and 0 deletions
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48
src/amd/vulkan/radv_cmd_buffer.h
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@ -293,15 +293,62 @@ enum rgp_flush_bits {
enum radv_tracked_reg {
RADV_TRACKED_DB_COUNT_CONTROL,
RADV_TRACKED_DB_SHADER_CONTROL,
RADV_TRACKED_DB_VRS_OVERRIDE_CNTL,
RADV_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
RADV_TRACKED_GE_NGG_SUBGRP_CNTL,
RADV_TRACKED_PA_CL_VRS_CNTL,
RADV_TRACKED_PA_CL_VS_OUT_CNTL,
RADV_TRACKED_PA_SC_BINNER_CNTL_0,
RADV_TRACKED_PA_SC_SHADER_CONTROL,
/* 2 consecutive registers */
RADV_TRACKED_SPI_PS_INPUT_ENA,
RADV_TRACKED_SPI_PS_INPUT_ADDR,
RADV_TRACKED_SPI_PS_IN_CONTROL,
/* 2 consecutive registers */
RADV_TRACKED_SPI_SHADER_IDX_FORMAT,
RADV_TRACKED_SPI_SHADER_POS_FORMAT,
RADV_TRACKED_SPI_SHADER_Z_FORMAT,
RADV_TRACKED_SPI_VS_OUT_CONFIG,
/* 3 consecutive registers */
RADV_TRACKED_SX_PS_DOWNCONVERT,
RADV_TRACKED_SX_BLEND_OPT_EPSILON,
RADV_TRACKED_SX_BLEND_OPT_CONTROL,
RADV_TRACKED_VGT_DRAW_PAYLOAD_CNTL,
RADV_TRACKED_VGT_ESGS_RING_ITEMSIZE, /* GFX6-8 */
RADV_TRACKED_VGT_GS_MODE,
RADV_TRACKED_VGT_GS_INSTANCE_CNT,
RADV_TRACKED_VGT_GS_ONCHIP_CNTL,
RADV_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
RADV_TRACKED_VGT_GS_MAX_VERT_OUT,
RADV_TRACKED_VGT_GS_OUT_PRIM_TYPE,
/* 4 consecutive registers */
RADV_TRACKED_VGT_GS_VERT_ITEMSIZE,
RADV_TRACKED_VGT_GS_VERT_ITEMSIZE_1,
RADV_TRACKED_VGT_GS_VERT_ITEMSIZE_2,
RADV_TRACKED_VGT_GS_VERT_ITEMSIZE_3,
RADV_TRACKED_VGT_GSVS_RING_ITEMSIZE,
/* 3 consecutive registers */
RADV_TRACKED_VGT_GSVS_RING_OFFSET_1,
RADV_TRACKED_VGT_GSVS_RING_OFFSET_2,
RADV_TRACKED_VGT_GSVS_RING_OFFSET_3,
RADV_TRACKED_VGT_MULTI_PRIM_IB_RESET_INDX, /* GFX6-7 */
RADV_TRACKED_VGT_PRIMITIVEID_EN,
RADV_TRACKED_VGT_REUSE_OFF,
RADV_TRACKED_VGT_SHADER_STAGES_EN,
RADV_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
RADV_NUM_ALL_TRACKED_REGS,
};
@ -309,6 +356,7 @@ enum radv_tracked_reg {
struct radv_tracked_regs {
BITSET_DECLARE(reg_saved_mask, RADV_NUM_ALL_TRACKED_REGS);
uint32_t reg_value[RADV_NUM_ALL_TRACKED_REGS];
uint32_t spi_ps_input_cntl[32];
};
struct radv_cmd_state {