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ac: Add maximum number of submitted IBs.

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The number of IBs per submit isn't infinite, it depends on the IP type
(ie. some initial setup needed for a submit) and the packet size.
It can be calculated according to the kernel source code as:
(ring->max_dw - emit_frame_size) / emit_ib_size

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>
This commit is contained in:
Timur Kristóf 2023-04-09 03:06:07 +02:00 • committed by Marge Bot
parent 87d22933ae
commit daeb409559
2 changed files with 25 additions and 0 deletions
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24
src/amd/common/ac_gpu_info.c
View file

@ -1434,6 +1434,24 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info)
}
}
/* The number of IBs per submit isn't infinite, it depends on the IP type
* (ie. some initial setup needed for a submit) and the packet size.
* It can be calculated according to the kernel source code as:
* (ring->max_dw - emit_frame_size) / emit_ib_size
*
* The numbers we chose here is a rough estimate that should
* work well (as of kernel 6.3).
*/
memset(info->max_submitted_ibs, 50, AMD_NUM_IP_TYPES);
info->max_submitted_ibs[AMD_IP_GFX] = info->gfx_level >= GFX7 ? 192 : 144;
info->max_submitted_ibs[AMD_IP_COMPUTE] = 124;
info->max_submitted_ibs[AMD_IP_VCN_JPEG] = 16;
for (unsigned i = 0; i < AMD_NUM_IP_TYPES; ++i) {
/* Clear out max submitted IB count for IPs that have no queues. */
if (!info->ip[i].num_queues)
info->max_submitted_ibs[i] = 0;
}
if (info->gfx_level >= GFX11) {
switch (info->family) {
case CHIP_GFX1103_R1:
@ -1691,6 +1709,12 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f)
fprintf(f, " mid_command_buffer_preemption_enabled = %u\n",
info->mid_command_buffer_preemption_enabled);
fprintf(f, " has_tmz_support = %u\n", info->has_tmz_support);
for (unsigned i = 0; i < AMD_NUM_IP_TYPES; i++) {
if (info->max_submitted_ibs[i]) {
fprintf(f, " IP %-7s max_submitted_ibs = %u\n", ip_string[i],
info->max_submitted_ibs[i]);
}
}
fprintf(f, "Shader core info:\n");
for (unsigned i = 0; i < info->max_se; i++) {

1
src/amd/common/ac_gpu_info.h
View file

@ -211,6 +211,7 @@ struct radeon_info {
uint32_t drm_major; /* version */
uint32_t drm_minor;
uint32_t drm_patchlevel;
uint8_t max_submitted_ibs[AMD_NUM_IP_TYPES];
bool is_amdgpu;
bool has_userptr;
bool has_syncobj;