fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-04-19 10:10:39 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radv: Create continue preamble on GFX6 even when no shader rings are used.

Browse source 
Skipping the continue preamble can allow other processes to mess
up some	registers set by the current process.

Originally, we could omit generating the continue preamble when
no shader rings were used, because the register initialization
happened at the beginning of every main cmdbuf. However, this
isn't the case anymore.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>
This commit is contained in:
Timur Kristóf 2023-04-03 17:47:10 +02:00 • committed by Marge Bot
parent 0bba139767
commit 87d22933ae
1 changed files with 0 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
src/amd/vulkan/radv_queue.c
View file

@ -1069,12 +1069,6 @@ radv_update_preamble_cs(struct radv_queue_state *queue, struct radv_device *devi
if (!(device->instance->debug_flags & RADV_DEBUG_NO_IBS) &&
device->physical_device->rad_info.gfx_level >= GFX7)
continue;
/* Continue preamble is unnecessary when no shader rings are used. */
if (!needs->scratch_size_per_wave && !needs->compute_scratch_size_per_wave &&
!needs->esgs_ring_size && !needs->gsvs_ring_size && !needs->tess_rings &&
!needs->task_rings && !needs->mesh_scratch_ring && !needs->attr_ring_size &&
!needs->gds && !needs->gds_oa && !needs->sample_positions)
continue;
}
enum rgp_flush_bits sqtt_flush_bits = 0;