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freedreno/a5xx: SP_BLEND_CNTL has per-mrt blend enable bit

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Blending in SP_BLEND_CNTL is not a binary flag but the same
mask as in RB_BLEND_CNTL. It is a per-mrt enable bit for blending.

Copied form a6xx, on a5xx it should be have the same since it seems
to have the same structure layout.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10682>
This commit is contained in:
Danylo Piliaiev 2021-05-07 13:03:36 +03:00 • committed by Marge Bot
parent 14da2444a9
commit daad8f2245
5 changed files with 10 additions and 9 deletions
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4
src/freedreno/.gitlab-ci/reference/crash.log
View file

@ -7379,7 +7379,7 @@ clusters:
00000000 SP_FS_PVT_MEM_ADDR: 0
00000000 SP_FS_PVT_MEM_ADDR_HI: 0
00000000 SP_FS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000100 SP_BLEND_CNTL: { UNK8 }
00000100 SP_BLEND_CNTL: { ENABLE_BLEND = 0 | UNK8 }
00000000 SP_SRGB_CNTL: { 0 }
00000000 SP_FS_RENDER_COMPONENTS: { RT0 = 0 | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
fcfcfc00 SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x }
@ -7461,7 +7461,7 @@ clusters:
00000000 SP_FS_PVT_MEM_ADDR: 0
00000000 SP_FS_PVT_MEM_ADDR_HI: 0
00000000 SP_FS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000100 SP_BLEND_CNTL: { UNK8 }
00000100 SP_BLEND_CNTL: { ENABLE_BLEND = 0 | UNK8 }
00000000 SP_SRGB_CNTL: { 0 }
00000000 SP_FS_RENDER_COMPONENTS: { RT0 = 0 | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
fcfcfc00 SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x }

4
src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
View file

@ -1162,7 +1162,7 @@ t4 write RB_MRT[0].CONTROL (8820)
RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_SRC_COLOR | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_DST_COLOR | ALPHA_SRC_FACTOR = FACTOR_SRC_COLOR | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_DST_COLOR }
0000000001054784: 0000: 40882002 00000780 08040804
t4 write SP_BLEND_CNTL (a989)
SP_BLEND_CNTL: { UNK8 }
SP_BLEND_CNTL: { ENABLE_BLEND = 0 | UNK8 }
0000000001054790: 0000: 40a98901 00000100
t4 write RB_BLEND_CNTL (8865)
RB_BLEND_CNTL: { ENABLE_BLEND = 0 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff }
@ -1502,7 +1502,7 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
- shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
+ 00000000 SP_FS_OBJ_START_HI: 0
!+ 00000100 SP_BLEND_CNTL: { UNK8 }
!+ 00000100 SP_BLEND_CNTL: { ENABLE_BLEND = 0 | UNK8 }
+ 00000000 SP_SRGB_CNTL: { 0 }
!+ 0000000f SP_FS_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
!+ fcfcfc00 SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x }

4
src/freedreno/.gitlab-ci/reference/fd-clouds.log
View file

@ -5157,7 +5157,7 @@ t4 write RB_DITHER_CNTL (880e)
RB_DITHER_CNTL: { DITHER_MODE_MRT0 = DITHER_ALWAYS | DITHER_MODE_MRT1 = DITHER_ALWAYS | DITHER_MODE_MRT2 = DITHER_ALWAYS | DITHER_MODE_MRT3 = DITHER_ALWAYS | DITHER_MODE_MRT4 = DITHER_ALWAYS | DITHER_MODE_MRT5 = DITHER_ALWAYS | DITHER_MODE_MRT6 = DITHER_ALWAYS | DITHER_MODE_MRT7 = DITHER_ALWAYS }
0000000001124080: 0000: 40880e01 00005555
t4 write SP_BLEND_CNTL (a989)
SP_BLEND_CNTL: { UNK8 }
SP_BLEND_CNTL: { ENABLE_BLEND = 0 | UNK8 }
0000000001124088: 0000: 40a98901 00000100
t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_8_BIT | PATCH_TYPE = TESS_QUADS }
@ -6728,7 +6728,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
- shaderdb: 1120 cat0, 48 cat1, 551 cat2, 512 cat3, 183 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 1326 sstall, 140 (ss), 0 (sy)
+ 00000000 SP_FS_OBJ_START_HI: 0
!+ 00000100 SP_BLEND_CNTL: { UNK8 }
!+ 00000100 SP_BLEND_CNTL: { ENABLE_BLEND = 0 | UNK8 }
+ fcfcfc00 SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x }
!+ 00000001 SP_FS_OUTPUT_CNTL1: { MRT = 1 }
!+ 00000004 SP_FS_OUTPUT[0].REG: { REGID = r1.x }

3
src/freedreno/registers/adreno/a5xx.xml
View file

@ -2527,7 +2527,8 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set
<reg32 offset="0xe5c3" name="SP_FS_OBJ_START_LO"/>
<reg32 offset="0xe5c4" name="SP_FS_OBJ_START_HI"/>
<reg32 offset="0xe5c9" name="SP_BLEND_CNTL">
<bitfield name="ENABLED" pos="0" type="boolean"/>
<!-- per-mrt enable bit -->
<bitfield name="ENABLE_BLEND" low="0" high="7"/>
<bitfield name="UNK8" pos="8" type="boolean"/>
<bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
</reg32>

4
src/gallium/drivers/freedreno/a5xx/fd5_blend.c
View file

@ -126,9 +126,9 @@ fd5_blend_state_create(struct pipe_context *pctx,
COND(cso->alpha_to_coverage, A5XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE) |
COND(cso->independent_blend_enable, A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND);
so->sp_blend_cntl =
A5XX_SP_BLEND_CNTL_ENABLE_BLEND(mrt_blend) |
A5XX_SP_BLEND_CNTL_UNK8 |
COND(cso->alpha_to_coverage, A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE) |
COND(mrt_blend, A5XX_SP_BLEND_CNTL_ENABLED);
COND(cso->alpha_to_coverage, A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE);
return so;
}