turnip,freedreno/a6xx: SP_BLEND_CNTL has per-mrt blend enable bit

Blending in SP_BLEND_CNTL is not a binary flag but the same
mask as in RB_BLEND_CNTL. It is a per-mrt enable bit for blending.

Example SP_BLEND_CNTL produced by blob on a630 and different MRT
blendings:
  SP_BLEND_CNTL: { UNK8 | 0x6 }
  SP_BLEND_CNTL: { ENABLED | UNK8 | 0xe }
(Decoded before this commit)

Fixes mis-rendering with D3D11 game "Spelunky 2".

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10682>
This commit is contained in:
Danylo Piliaiev 2021-05-07 12:45:47 +03:00 committed by Marge Bot
parent 39a938ecf4
commit 14da2444a9
3 changed files with 5 additions and 4 deletions

View file

@ -2987,7 +2987,8 @@ to upconvert to 32b float internally?
<reg32 offset="0xa988" name="SP_FS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
<reg32 offset="0xa989" name="SP_BLEND_CNTL">
<bitfield name="ENABLED" pos="0" type="boolean"/>
<!-- per-mrt enable bit -->
<bitfield name="ENABLE_BLEND" low="0" high="7"/>
<bitfield name="UNK8" pos="8" type="boolean"/>
<bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
<bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>

View file

@ -1998,7 +1998,7 @@ tu6_emit_blend_control(struct tu_cs *cs,
: ((1 << msaa_info->rasterizationSamples) - 1);
tu_cs_emit_regs(cs,
A6XX_SP_BLEND_CNTL(.enabled = blend_enable_mask,
A6XX_SP_BLEND_CNTL(.enable_blend = blend_enable_mask,
.dual_color_in_enable = dual_src_blend,
.alpha_to_coverage = msaa_info->alphaToCoverageEnable,
.unk8 = true));

View file

@ -125,9 +125,9 @@ __fd6_setup_blend_variant(struct fd6_blend_stateobj *blend,
.dither_mode_mrt7 =
cso->dither ? DITHER_ALWAYS : DITHER_DISABLE, ));
OUT_REG(ring, A6XX_SP_BLEND_CNTL(.unk8 = true,
OUT_REG(ring, A6XX_SP_BLEND_CNTL(.enable_blend = mrt_blend,
.unk8 = true,
.alpha_to_coverage = cso->alpha_to_coverage,
.enabled = !!mrt_blend,
.dual_color_in_enable =
blend->use_dual_src_blend, ));