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intel/brw: Remove extra stage_prog_data field in fs_visitor

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Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27861>
This commit is contained in:
Caio Oliveira 2024-02-19 23:07:04 -08:00 • committed by Marge Bot
parent 634dff403f
commit d9552fccf2
7 changed files with 18 additions and 20 deletions
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18
src/intel/compiler/brw_fs.cpp
View file

@ -1188,13 +1188,13 @@ fs_visitor::emit_gs_thread_end()
void
fs_visitor::assign_curb_setup()
{
unsigned uniform_push_length = DIV_ROUND_UP(stage_prog_data->nr_params, 8);
unsigned uniform_push_length = DIV_ROUND_UP(prog_data->nr_params, 8);
unsigned ubo_push_length = 0;
unsigned ubo_push_start[4];
for (int i = 0; i < 4; i++) {
ubo_push_start[i] = 8 * (ubo_push_length + uniform_push_length);
ubo_push_length += stage_prog_data->ubo_ranges[i].length;
ubo_push_length += prog_data->ubo_ranges[i].length;
}
prog_data->curb_read_length = uniform_push_length + ubo_push_length;
@ -1307,13 +1307,13 @@ fs_visitor::assign_curb_setup()
}
}
uint64_t want_zero = used & stage_prog_data->zero_push_reg;
uint64_t want_zero = used & prog_data->zero_push_reg;
if (want_zero) {
fs_builder ubld = fs_builder(this, 8).exec_all().at(
cfg->first_block(), cfg->first_block()->start());
/* push_reg_mask_param is in 32-bit units */
unsigned mask_param = stage_prog_data->push_reg_mask_param;
unsigned mask_param = prog_data->push_reg_mask_param;
struct brw_reg mask = brw_vec1_grf(payload().num_regs + mask_param / 8,
mask_param % 8);
@ -1946,7 +1946,7 @@ fs_visitor::assign_constant_locations()
* brw_curbe.c/crocus_state.c
*/
const unsigned max_push_length = 64;
unsigned push_length = DIV_ROUND_UP(stage_prog_data->nr_params, 8);
unsigned push_length = DIV_ROUND_UP(prog_data->nr_params, 8);
for (int i = 0; i < 4; i++) {
struct brw_ubo_range *range = &prog_data->ubo_ranges[i];
@ -2057,7 +2057,7 @@ brw_sample_mask_reg(const fs_builder &bld)
if (s.stage != MESA_SHADER_FRAGMENT) {
return brw_imm_ud(0xffffffff);
} else if (brw_wm_prog_data(s.stage_prog_data)->uses_kill) {
} else if (brw_wm_prog_data(s.prog_data)->uses_kill) {
assert(bld.dispatch_width() <= 16);
return brw_flag_subreg(sample_mask_flag_subreg(s) + bld.group() / 16);
} else {
@ -2111,7 +2111,7 @@ brw_emit_predicate_on_sample_mask(const fs_builder &bld, fs_inst *inst)
const fs_reg sample_mask = brw_sample_mask_reg(bld);
const unsigned subreg = sample_mask_flag_subreg(s);
if (brw_wm_prog_data(s.stage_prog_data)->uses_kill) {
if (brw_wm_prog_data(s.prog_data)->uses_kill) {
assert(sample_mask.file == ARF &&
sample_mask.nr == brw_flag_subreg(subreg).nr &&
sample_mask.subnr == brw_flag_subreg(
@ -4183,11 +4183,11 @@ brw_fs_test_dispatch_packing(const fs_builder &bld)
const gl_shader_stage stage = shader->stage;
const bool uses_vmask =
stage == MESA_SHADER_FRAGMENT &&
brw_wm_prog_data(shader->stage_prog_data)->uses_vmask;
brw_wm_prog_data(shader->prog_data)->uses_vmask;
if (brw_stage_has_packed_dispatch(shader->devinfo, stage,
shader->max_polygons,
shader->stage_prog_data)) {
shader->prog_data)) {
const fs_builder ubld = bld.exec_all().group(1, 0);
const fs_reg tmp = component(bld.vgrf(BRW_REGISTER_TYPE_UD), 0);
const fs_reg mask = uses_vmask ? brw_vmask_reg() : brw_dmask_reg();

1
src/intel/compiler/brw_fs.h
View file

@ -305,7 +305,6 @@ public:
const struct intel_device_info * const devinfo;
const nir_shader *nir;
struct brw_stage_prog_data * const stage_prog_data;
/** ralloc context for temporary data used during compile */
void *mem_ctx;

4
src/intel/compiler/brw_fs_lower.cpp
View file

@ -405,10 +405,10 @@ brw_fs_lower_find_live_channel(fs_visitor &s)
bool packed_dispatch =
brw_stage_has_packed_dispatch(s.devinfo, s.stage, s.max_polygons,
s.stage_prog_data);
s.prog_data);
bool vmask =
s.stage == MESA_SHADER_FRAGMENT &&
brw_wm_prog_data(s.stage_prog_data)->uses_vmask;
brw_wm_prog_data(s.prog_data)->uses_vmask;
foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) {
if (inst->opcode != SHADER_OPCODE_FIND_LIVE_CHANNEL &&

4
src/intel/compiler/brw_fs_nir.cpp
View file

@ -2082,7 +2082,7 @@ emit_pixel_interpolater_send(const fs_builder &bld,
glsl_interp_mode interpolation)
{
struct brw_wm_prog_data *wm_prog_data =
brw_wm_prog_data(bld.shader->stage_prog_data);
brw_wm_prog_data(bld.shader->prog_data);
fs_reg srcs[INTERP_NUM_SRCS];
srcs[INTERP_SRC_OFFSET] = src;
@ -3794,7 +3794,7 @@ emit_shading_rate_setup(nir_to_brw_state &ntb)
assert(devinfo->ver >= 11);
struct brw_wm_prog_data *wm_prog_data =
brw_wm_prog_data(bld.shader->stage_prog_data);
brw_wm_prog_data(bld.shader->prog_data);
/* Coarse pixel shading size fields overlap with other fields of not in
* coarse pixel dispatch mode, so report 0 when that's not the case.

2
src/intel/compiler/brw_fs_opt.cpp
View file

@ -398,7 +398,7 @@ brw_fs_opt_eliminate_find_live_channel(fs_visitor &s)
unsigned depth = 0;
if (!brw_stage_has_packed_dispatch(s.devinfo, s.stage, s.max_polygons,
s.stage_prog_data)) {
s.prog_data)) {
/* The optimization below assumes that channel zero is live on thread
* dispatch, which may not be the case if the fixed function dispatches
* threads sparsely.

2
src/intel/compiler/brw_fs_thread_payload.cpp
View file

@ -363,7 +363,7 @@ cs_thread_payload::load_subgroup_id(const fs_builder &bld,
assert(devinfo->verx10 < 125);
assert(gl_shader_stage_is_compute(bld.shader->stage));
int index = brw_get_subgroup_id_param_index(devinfo,
bld.shader->stage_prog_data);
bld.shader->prog_data);
bld.MOV(dest, fs_reg(UNIFORM, index, BRW_REGISTER_TYPE_UD));
}
}

7
src/intel/compiler/brw_fs_visitor.cpp
View file

@ -988,7 +988,7 @@ fs_visitor::fs_visitor(const struct brw_compiler *compiler,
bool debug_enabled)
: compiler(compiler), log_data(params->log_data),
devinfo(compiler->devinfo), nir(shader),
stage_prog_data(prog_data), mem_ctx(params->mem_ctx),
mem_ctx(params->mem_ctx),
cfg(NULL), stage(shader->info.stage),
debug_enabled(debug_enabled),
key(key), gs_compile(NULL), prog_data(prog_data),
@ -1012,7 +1012,7 @@ fs_visitor::fs_visitor(const struct brw_compiler *compiler,
bool debug_enabled)
: compiler(compiler), log_data(params->log_data),
devinfo(compiler->devinfo), nir(shader),
stage_prog_data(&prog_data->base), mem_ctx(params->mem_ctx),
mem_ctx(params->mem_ctx),
cfg(NULL), stage(shader->info.stage),
debug_enabled(debug_enabled),
key(&key->base), gs_compile(NULL), prog_data(&prog_data->base),
@ -1039,7 +1039,7 @@ fs_visitor::fs_visitor(const struct brw_compiler *compiler,
bool debug_enabled)
: compiler(compiler), log_data(params->log_data),
devinfo(compiler->devinfo), nir(shader),
stage_prog_data(&prog_data->base.base), mem_ctx(params->mem_ctx),
mem_ctx(params->mem_ctx),
cfg(NULL), stage(shader->info.stage),
debug_enabled(debug_enabled),
key(&c->key.base), gs_compile(c),
@ -1062,7 +1062,6 @@ void
fs_visitor::init()
{
this->max_dispatch_width = 32;
this->prog_data = this->stage_prog_data;
this->failed = false;
this->fail_msg = NULL;