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ilo: add some MI commands to GPE

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We will need MI commands that load/store registers.
This commit is contained in:
Chia-I Wu 2014-03-02 11:59:26 +08:00
parent 0f41f9c63d
commit d8b2e3c25e
4 changed files with 116 additions and 0 deletions
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4
src/gallium/drivers/ilo/ilo_gpe_gen6.c
View file

@ -2581,6 +2581,10 @@ ilo_gpe_gen6_estimate_command_size(const struct ilo_dev_info *dev,
int header;
int body;
} gen6_command_size_table[ILO_GPE_GEN6_COMMAND_COUNT] = {
[ILO_GPE_GEN6_MI_STORE_DATA_IMM] = { 0, 5 },
[ILO_GPE_GEN6_MI_LOAD_REGISTER_IMM] = { 0, 3 },
[ILO_GPE_GEN6_MI_STORE_REGISTER_MEM] = { 0, 3 },
[ILO_GPE_GEN6_MI_REPORT_PERF_COUNT] = { 0, 3 },
[ILO_GPE_GEN6_STATE_BASE_ADDRESS] = { 0, 10 },
[ILO_GPE_GEN6_STATE_SIP] = { 0, 2 },
[ILO_GPE_GEN6_3DSTATE_VF_STATISTICS] = { 0, 1 },

104
src/gallium/drivers/ilo/ilo_gpe_gen6.h
View file

@ -42,6 +42,8 @@
#define ILO_GPE_VALID_GEN(dev, min_gen, max_gen) \
assert((dev)->gen >= ILO_GEN(min_gen) && (dev)->gen <= ILO_GEN(max_gen))
#define ILO_GPE_MI(op) (0x0 << 29 | (op) << 23)
#define ILO_GPE_CMD(pipeline, op, subop) \
(0x3 << 29 | (pipeline) << 27 | (op) << 24 | (subop) << 16)
@ -49,6 +51,10 @@
* Commands that GEN6 GPE could emit.
*/
enum ilo_gpe_gen6_command {
ILO_GPE_GEN6_MI_STORE_DATA_IMM, /* ILO_GPE_MI(0x20) */
ILO_GPE_GEN6_MI_LOAD_REGISTER_IMM, /* ILO_GPE_MI(0x22) */
ILO_GPE_GEN6_MI_STORE_REGISTER_MEM, /* ILO_GPE_MI(0x24) */
ILO_GPE_GEN6_MI_REPORT_PERF_COUNT, /* ILO_GPE_MI(0x28) */
ILO_GPE_GEN6_STATE_BASE_ADDRESS, /* (0x0, 0x1, 0x01) */
ILO_GPE_GEN6_STATE_SIP, /* (0x0, 0x1, 0x02) */
ILO_GPE_GEN6_3DSTATE_VF_STATISTICS, /* (0x1, 0x0, 0x0b) */
@ -336,6 +342,104 @@ ilo_gpe_gen6_fill_3dstate_sf_sbe(const struct ilo_dev_info *dev,
dw[12] = 0;
}
static inline void
gen6_emit_MI_STORE_DATA_IMM(const struct ilo_dev_info *dev,
struct intel_bo *bo, uint32_t bo_offset,
uint64_t val, bool store_qword,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_MI(0x20);
const uint8_t cmd_len = (store_qword) ? 5 : 4;
/* must use GGTT on GEN6 as in PIPE_CONTROL */
const uint32_t cmd_flags = (dev->gen == ILO_GEN(6)) ? (1 << 22) : 0;
const uint32_t read_domains = INTEL_DOMAIN_INSTRUCTION;
const uint32_t write_domain = INTEL_DOMAIN_INSTRUCTION;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
assert(bo_offset % ((store_qword) ? 8 : 4) == 0);
ilo_cp_begin(cp, cmd_len);
ilo_cp_write(cp, cmd | cmd_flags | (cmd_len - 2));
ilo_cp_write(cp, 0);
ilo_cp_write_bo(cp, bo_offset, bo, read_domains, write_domain);
ilo_cp_write(cp, (uint32_t) val);
if (store_qword)
ilo_cp_write(cp, (uint32_t) (val >> 32));
else
assert(val == (uint64_t) ((uint32_t) val));
ilo_cp_end(cp);
}
static inline void
gen6_emit_MI_LOAD_REGISTER_IMM(const struct ilo_dev_info *dev,
uint32_t reg, uint32_t val,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_MI(0x22);
const uint8_t cmd_len = 3;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
assert(reg % 4 == 0);
ilo_cp_begin(cp, cmd_len);
ilo_cp_write(cp, cmd | (cmd_len - 2));
ilo_cp_write(cp, reg);
ilo_cp_write(cp, val);
ilo_cp_end(cp);
}
static inline void
gen6_emit_MI_STORE_REGISTER_MEM(const struct ilo_dev_info *dev,
struct intel_bo *bo, uint32_t bo_offset,
uint32_t reg, struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_MI(0x24);
const uint8_t cmd_len = 3;
/* must use GGTT on GEN6 as in PIPE_CONTROL */
const uint32_t cmd_flags = (dev->gen == ILO_GEN(6)) ? (1 << 22) : 0;
const uint32_t read_domains = INTEL_DOMAIN_INSTRUCTION;
const uint32_t write_domain = INTEL_DOMAIN_INSTRUCTION;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
assert(reg % 4 == 0 && bo_offset % 4 == 0);
ilo_cp_begin(cp, cmd_len);
ilo_cp_write(cp, cmd | cmd_flags | (cmd_len - 2));
ilo_cp_write(cp, reg);
ilo_cp_write_bo(cp, bo_offset, bo, read_domains, write_domain);
ilo_cp_end(cp);
}
static inline void
gen6_emit_MI_REPORT_PERF_COUNT(const struct ilo_dev_info *dev,
struct intel_bo *bo, uint32_t bo_offset,
uint32_t report_id, struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_MI(0x28);
const uint8_t cmd_len = 3;
const uint32_t read_domains = INTEL_DOMAIN_INSTRUCTION;
const uint32_t write_domain = INTEL_DOMAIN_INSTRUCTION;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
assert(bo_offset % 64 == 0);
/* must use GGTT on GEN6 as in PIPE_CONTROL */
if (dev->gen == ILO_GEN(6))
bo_offset |= 0x1;
ilo_cp_begin(cp, cmd_len);
ilo_cp_write(cp, cmd | (cmd_len - 2));
ilo_cp_write_bo(cp, bo_offset, bo, read_domains, write_domain);
ilo_cp_write(cp, report_id);
ilo_cp_end(cp);
}
static inline void
gen6_emit_STATE_BASE_ADDRESS(const struct ilo_dev_info *dev,
struct intel_bo *general_state_bo,

4
src/gallium/drivers/ilo/ilo_gpe_gen7.c
View file

@ -679,6 +679,10 @@ ilo_gpe_gen7_estimate_command_size(const struct ilo_dev_info *dev,
int header;
int body;
} gen7_command_size_table[ILO_GPE_GEN7_COMMAND_COUNT] = {
[ILO_GPE_GEN7_MI_STORE_DATA_IMM] = { 0, 5 },
[ILO_GPE_GEN7_MI_LOAD_REGISTER_IMM] = { 0, 3 },
[ILO_GPE_GEN7_MI_STORE_REGISTER_MEM] = { 0, 3 },
[ILO_GPE_GEN7_MI_REPORT_PERF_COUNT] = { 0, 3 },
[ILO_GPE_GEN7_STATE_BASE_ADDRESS] = { 0, 10 },
[ILO_GPE_GEN7_STATE_SIP] = { 0, 2 },
[ILO_GPE_GEN7_3DSTATE_VF_STATISTICS] = { 0, 1 },

4
src/gallium/drivers/ilo/ilo_gpe_gen7.h
View file

@ -40,6 +40,10 @@
* Commands that GEN7 GPE could emit.
*/
enum ilo_gpe_gen7_command {
ILO_GPE_GEN7_MI_STORE_DATA_IMM, /* ILO_GPE_MI(0x20) */
ILO_GPE_GEN7_MI_LOAD_REGISTER_IMM, /* ILO_GPE_MI(0x22) */
ILO_GPE_GEN7_MI_STORE_REGISTER_MEM, /* ILO_GPE_MI(0x24) */
ILO_GPE_GEN7_MI_REPORT_PERF_COUNT, /* ILO_GPE_MI(0x28) */
ILO_GPE_GEN7_STATE_BASE_ADDRESS, /* (0x0, 0x1, 0x01) */
ILO_GPE_GEN7_STATE_SIP, /* (0x0, 0x1, 0x02) */
ILO_GPE_GEN7_3DSTATE_VF_STATISTICS, /* (0x1, 0x0, 0x0b) */