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ilo: set PIPE_CONTROL_GLOBAL_GTT_WRITE automatically

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Set the flag automatically in gen6_emit_PIPE_CONTROL(), and set it only for
GEN6.
This commit is contained in:
Chia-I Wu 2014-03-02 12:15:17 +08:00
parent 345bf92f13
commit 0f41f9c63d
2 changed files with 16 additions and 2 deletions
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4
src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c
View file

@ -1506,7 +1506,7 @@ ilo_3d_pipeline_emit_write_timestamp_gen6(struct ilo_3d_pipeline *p,
gen6_emit_PIPE_CONTROL(p->dev,
PIPE_CONTROL_WRITE_TIMESTAMP,
bo, index * sizeof(uint64_t) | PIPE_CONTROL_GLOBAL_GTT_WRITE,
bo, index * sizeof(uint64_t),
true, p->cp);
}
@ -1520,7 +1520,7 @@ ilo_3d_pipeline_emit_write_depth_count_gen6(struct ilo_3d_pipeline *p,
gen6_emit_PIPE_CONTROL(p->dev,
PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_WRITE_DEPTH_COUNT,
bo, index * sizeof(uint64_t) | PIPE_CONTROL_GLOBAL_GTT_WRITE,
bo, index * sizeof(uint64_t),
true, p->cp);
}

14
src/gallium/drivers/ilo/ilo_gpe_gen6.h
View file

@ -1769,6 +1769,8 @@ gen6_emit_PIPE_CONTROL(const struct ilo_dev_info *dev,
ILO_GPE_VALID_GEN(dev, 6, 7.5);
assert(bo_offset % ((write_qword) ? 8 : 4) == 0);
if (dw1 & PIPE_CONTROL_CS_STALL) {
/*
* From the Sandy Bridge PRM, volume 2 part 1, page 73:
@ -1821,6 +1823,18 @@ gen6_emit_PIPE_CONTROL(const struct ilo_dev_info *dev,
PIPE_CONTROL_DEPTH_CACHE_FLUSH)));
}
/*
* From the Sandy Bridge PRM, volume 1 part 3, page 19:
*
* "[DevSNB] PPGTT memory writes by MI_* (such as MI_STORE_DATA_IMM)
* and PIPE_CONTROL are not supported."
*
* The kernel will add the mapping automatically (when write domain is
* INTEL_DOMAIN_INSTRUCTION).
*/
if (dev->gen == ILO_GEN(6) && bo)
bo_offset |= PIPE_CONTROL_GLOBAL_GTT_WRITE;
ilo_cp_begin(cp, cmd_len);
ilo_cp_write(cp, cmd | (cmd_len - 2));
ilo_cp_write(cp, dw1);