From d5d4604aa683f4ae23c66a3295d1c507fb80ab18 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tapani=20P=C3=A4lli?= Date: Wed, 11 May 2022 12:54:41 +0300 Subject: [PATCH] intel/genxml: add VFG_PREEMPTION_CHICKEN_BITS register MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This can be used to disable batch preemption on DG2+ either completely or with selected primitive topologies. Commit adds bit explicitly for Polygon, Trifan and LineLoop topologies for Wa_14015207028. Signed-off-by: Tapani Pälli Reviewed-by: José Roberto de Souza Part-of: --- src/intel/genxml/gen125.xml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml index f2c55c6f8c0..b7972becdf7 100644 --- a/src/intel/genxml/gen125.xml +++ b/src/intel/genxml/gen125.xml @@ -8086,6 +8086,13 @@ + + + + + + +