fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-04 22:49:13 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

anv: convert Wa_14010455700 to use workaround mechanism

Browse source 
The original lineage for 14010455700 is 1808121037.  Use this defect
number to apply the workaround to relevant platforms with the new
workaround mechanism.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23380>
This commit is contained in:
Mark Janes 2023-06-05 10:13:19 -07:00 • committed by Marge Bot
parent 7868c8698f
commit d57eedefa9
1 changed files with 4 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -3968,7 +3968,7 @@ genX(CmdExecuteCommands)(
if (secondary->perf_query_pool)
primary->perf_query_pool = secondary->perf_query_pool;
#if GFX_VERx10 == 120
#if INTEL_NEEDS_WA_1808121037
if (secondary->state.depth_reg_mode != ANV_DEPTH_REG_MODE_UNKNOWN)
primary->state.depth_reg_mode = secondary->state.depth_reg_mode;
#endif
@ -6794,7 +6794,7 @@ void
genX(cmd_buffer_emit_gfx12_depth_wa)(struct anv_cmd_buffer *cmd_buffer,
const struct isl_surf *surf)
{
#if GFX_VERx10 == 120
#if INTEL_NEEDS_WA_1808121037
const bool is_d16_1x_msaa = surf->format == ISL_FORMAT_R16_UNORM &&
surf->samples == 1;
@ -6819,10 +6819,10 @@ genX(cmd_buffer_emit_gfx12_depth_wa)(struct anv_cmd_buffer *cmd_buffer,
ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
ANV_PIPE_DEPTH_STALL_BIT |
ANV_PIPE_END_OF_PIPE_SYNC_BIT,
"Workaround: Stop pipeline for 14010455700");
"Workaround: Stop pipeline for 1808121037");
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
/* Wa_14010455700
/* Wa_1808121037
*
* To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer
* Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA”.