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iris: convert Wa_14010455700 to use workaround mechanism
The original lineage for 14010455700 is 1808121037. Use this defect number to apply the workaround to relevant platforms with the new workaround mechanism. Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23380>
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1 changed files with 6 additions and 6 deletions
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@ -1360,7 +1360,7 @@ struct iris_depth_buffer_state {
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GENX(3DSTATE_CLEAR_PARAMS_length)];
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};
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#if GFX_VERx10 == 120
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#if INTEL_NEEDS_WA_1808121037
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enum iris_depth_reg_mode {
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IRIS_DEPTH_REG_MODE_HW_DEFAULT = 0,
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IRIS_DEPTH_REG_MODE_D16_1X_MSAA,
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@ -1389,7 +1389,7 @@ struct iris_genx_state {
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/* Is object level preemption enabled? */
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bool object_preemption;
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#if GFX_VERx10 == 120
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#if INTEL_NEEDS_WA_1808121037
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enum iris_depth_reg_mode depth_reg_mode;
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#endif
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@ -6069,7 +6069,7 @@ genX(emit_depth_state_workarounds)(struct iris_context *ice,
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struct iris_batch *batch,
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const struct isl_surf *surf)
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{
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#if GFX_VERx10 == 120
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#if INTEL_NEEDS_WA_1808121037
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const bool is_d16_1x_msaa = surf->format == ISL_FORMAT_R16_UNORM &&
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surf->samples == 1;
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@ -6091,11 +6091,11 @@ genX(emit_depth_state_workarounds)(struct iris_context *ice,
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* settings while we change the registers.
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*/
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iris_emit_end_of_pipe_sync(batch,
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"Workaround: Stop pipeline for 14010455700",
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"Workaround: Stop pipeline for Wa_1808121037",
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PIPE_CONTROL_DEPTH_STALL |
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PIPE_CONTROL_DEPTH_CACHE_FLUSH);
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/* Wa_14010455700
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/* Wa_1808121037
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*
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* To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer
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* Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA”.
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@ -8813,7 +8813,7 @@ iris_lost_genx_state(struct iris_context *ice, struct iris_batch *batch)
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{
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struct iris_genx_state *genx = ice->state.genx;
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#if GFX_VERx10 == 120
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#if INTEL_NEEDS_WA_1808121037
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genx->depth_reg_mode = IRIS_DEPTH_REG_MODE_UNKNOWN;
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#endif
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