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nir: add ACCESS_CP_GE_COHERENT_AMD

Browse source 
required by amd gfx12

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-By: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28889>
This commit is contained in:
Marek Olšák 2023-05-31 14:52:31 -04:00 • committed by Marge Bot
parent 7187373ec2
commit d4cfcbdde8
4 changed files with 13 additions and 5 deletions
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2
src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c
View file

@ -126,7 +126,7 @@ task_write_draw_ring(nir_builder *b,
nir_store_buffer_amd(b, store_val, ring, vector_off, scalar_off, zero,
.base = const_off, .memory_modes = nir_var_shader_out,
.access = ACCESS_COHERENT);
.access = ACCESS_COHERENT | ACCESS_CP_GE_COHERENT_AMD);
}
static bool

9
src/amd/common/ac_nir_lower_tess_io_to_mem.c
View file

@ -750,17 +750,18 @@ hs_store_tess_factors_for_tessellator(nir_builder *b, enum amd_gfx_level gfx_lev
/* LINES reversal */
nir_def *t = nir_vec2(b, nir_channel(b, tf_outer, 1), nir_channel(b, tf_outer, 0));
nir_store_buffer_amd(b, t, tessfactor_ring, tess_factors_offset, tess_factors_base, zero,
.base = tess_factors_const_offset, .access = ACCESS_COHERENT);
.base = tess_factors_const_offset, .access = ACCESS_COHERENT | ACCESS_CP_GE_COHERENT_AMD);
} else if (prim_mode == TESS_PRIMITIVE_TRIANGLES) {
nir_def *t = nir_vec4(b, nir_channel(b, tf_outer, 0), nir_channel(b, tf_outer, 1),
nir_channel(b, tf_outer, 2), nir_channel(b, tf_inner, 0));
nir_store_buffer_amd(b, t, tessfactor_ring, tess_factors_offset, tess_factors_base, zero,
.base = tess_factors_const_offset, .access = ACCESS_COHERENT);
.base = tess_factors_const_offset, .access = ACCESS_COHERENT | ACCESS_CP_GE_COHERENT_AMD);
} else {
nir_store_buffer_amd(b, tf_outer, tessfactor_ring, tess_factors_offset, tess_factors_base, zero,
.base = tess_factors_const_offset, .access = ACCESS_COHERENT);
.base = tess_factors_const_offset, .access = ACCESS_COHERENT | ACCESS_CP_GE_COHERENT_AMD);
nir_store_buffer_amd(b, tf_inner, tessfactor_ring, tess_factors_offset, tess_factors_base, zero,
.base = tess_factors_const_offset + 4u * outer_comps, .access = ACCESS_COHERENT);
.base = tess_factors_const_offset + 4u * outer_comps,
.access = ACCESS_COHERENT | ACCESS_CP_GE_COHERENT_AMD);
}
}

1
src/compiler/nir/nir_print.c
View file

@ -797,6 +797,7 @@ print_access(enum gl_access_qualifier access, print_state *state, const char *se
{ ACCESS_CAN_SPECULATE, "speculatable" },
{ ACCESS_NON_TEMPORAL, "non-temporal" },
{ ACCESS_INCLUDE_HELPERS, "include-helpers" },
{ ACCESS_CP_GE_COHERENT_AMD, "cp-ge-coherent-amd" },
};
bool first = true;

6
src/compiler/shader_enums.h
View file

@ -1134,6 +1134,12 @@ enum gl_access_qualifier
* if MMU faults are suppressed for the load.
*/
ACCESS_CAN_SPECULATE = (1 << 12),
/**
* Whether coherency with CP (command processor) or GE (geometry engine)
* is required.
*/
ACCESS_CP_GE_COHERENT_AMD = (1 << 13),
};
/**