From d4cfcbdde8fdc350d778ca1020038b1ff33c444b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Wed, 31 May 2023 14:52:31 -0400 Subject: [PATCH] nir: add ACCESS_CP_GE_COHERENT_AMD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit required by amd gfx12 Reviewed-by: Timur Kristóf Acked-By: Georg Lehmann Part-of: --- src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c | 2 +- src/amd/common/ac_nir_lower_tess_io_to_mem.c | 9 +++++---- src/compiler/nir/nir_print.c | 1 + src/compiler/shader_enums.h | 6 ++++++ 4 files changed, 13 insertions(+), 5 deletions(-) diff --git a/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c b/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c index 9c81ca8fe30..8bd5020e95f 100644 --- a/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c +++ b/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c @@ -126,7 +126,7 @@ task_write_draw_ring(nir_builder *b, nir_store_buffer_amd(b, store_val, ring, vector_off, scalar_off, zero, .base = const_off, .memory_modes = nir_var_shader_out, - .access = ACCESS_COHERENT); + .access = ACCESS_COHERENT | ACCESS_CP_GE_COHERENT_AMD); } static bool diff --git a/src/amd/common/ac_nir_lower_tess_io_to_mem.c b/src/amd/common/ac_nir_lower_tess_io_to_mem.c index 704d9285f78..e5975e40514 100644 --- a/src/amd/common/ac_nir_lower_tess_io_to_mem.c +++ b/src/amd/common/ac_nir_lower_tess_io_to_mem.c @@ -750,17 +750,18 @@ hs_store_tess_factors_for_tessellator(nir_builder *b, enum amd_gfx_level gfx_lev /* LINES reversal */ nir_def *t = nir_vec2(b, nir_channel(b, tf_outer, 1), nir_channel(b, tf_outer, 0)); nir_store_buffer_amd(b, t, tessfactor_ring, tess_factors_offset, tess_factors_base, zero, - .base = tess_factors_const_offset, .access = ACCESS_COHERENT); + .base = tess_factors_const_offset, .access = ACCESS_COHERENT | ACCESS_CP_GE_COHERENT_AMD); } else if (prim_mode == TESS_PRIMITIVE_TRIANGLES) { nir_def *t = nir_vec4(b, nir_channel(b, tf_outer, 0), nir_channel(b, tf_outer, 1), nir_channel(b, tf_outer, 2), nir_channel(b, tf_inner, 0)); nir_store_buffer_amd(b, t, tessfactor_ring, tess_factors_offset, tess_factors_base, zero, - .base = tess_factors_const_offset, .access = ACCESS_COHERENT); + .base = tess_factors_const_offset, .access = ACCESS_COHERENT | ACCESS_CP_GE_COHERENT_AMD); } else { nir_store_buffer_amd(b, tf_outer, tessfactor_ring, tess_factors_offset, tess_factors_base, zero, - .base = tess_factors_const_offset, .access = ACCESS_COHERENT); + .base = tess_factors_const_offset, .access = ACCESS_COHERENT | ACCESS_CP_GE_COHERENT_AMD); nir_store_buffer_amd(b, tf_inner, tessfactor_ring, tess_factors_offset, tess_factors_base, zero, - .base = tess_factors_const_offset + 4u * outer_comps, .access = ACCESS_COHERENT); + .base = tess_factors_const_offset + 4u * outer_comps, + .access = ACCESS_COHERENT | ACCESS_CP_GE_COHERENT_AMD); } } diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c index bf7304e0d2a..7c2a84502ba 100644 --- a/src/compiler/nir/nir_print.c +++ b/src/compiler/nir/nir_print.c @@ -797,6 +797,7 @@ print_access(enum gl_access_qualifier access, print_state *state, const char *se { ACCESS_CAN_SPECULATE, "speculatable" }, { ACCESS_NON_TEMPORAL, "non-temporal" }, { ACCESS_INCLUDE_HELPERS, "include-helpers" }, + { ACCESS_CP_GE_COHERENT_AMD, "cp-ge-coherent-amd" }, }; bool first = true; diff --git a/src/compiler/shader_enums.h b/src/compiler/shader_enums.h index 89d6701436e..1ba4ca19cb0 100644 --- a/src/compiler/shader_enums.h +++ b/src/compiler/shader_enums.h @@ -1134,6 +1134,12 @@ enum gl_access_qualifier * if MMU faults are suppressed for the load. */ ACCESS_CAN_SPECULATE = (1 << 12), + + /** + * Whether coherency with CP (command processor) or GE (geometry engine) + * is required. + */ + ACCESS_CP_GE_COHERENT_AMD = (1 << 13), }; /**