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intel/isl: Setting L1 caching policy to Write-back mode

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For a RW L1 cache, both reads and writes are cached in the L1, at high
priority (MRU position). For a RO L1 cache, reads are cached at higher
priority and writes bypass the cache.

v1: (Ken)
- Set caching policy for buffer surfaces too

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16905>
This commit is contained in:
Sagar Ghuge 2021-08-12 11:53:47 -07:00 • committed by Lionel Landwerlin
parent 5e21f47428
commit d4b2b769d1
1 changed files with 10 additions and 0 deletions
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10
src/intel/isl/isl_surface_state.c
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@ -376,6 +376,11 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
s.MipTailStartLOD = 15;
#endif
#if GFX_VERx10 >= 125
/* Setting L1 caching policy to Write-back mode. */
s.L1CacheControl = L1CC_WB;
#endif
#if GFX_VER >= 6
const struct isl_extent3d image_align =
isl_get_image_alignment(info->surf);
@ -912,6 +917,11 @@ isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state,
s.MOCS = info->mocs;
#endif
#if GFX_VERx10 >= 125
/* Setting L1 caching policy to Write-back mode. */
s.L1CacheControl = L1CC_WB;
#endif
#if (GFX_VERx10 >= 75)
s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->swizzle.r;
s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->swizzle.g;