From d4b2b769d1dd55b6a2f587b9da91c3e451d3a71e Mon Sep 17 00:00:00 2001 From: Sagar Ghuge Date: Thu, 12 Aug 2021 11:53:47 -0700 Subject: [PATCH] intel/isl: Setting L1 caching policy to Write-back mode For a RW L1 cache, both reads and writes are cached in the L1, at high priority (MRU position). For a RO L1 cache, reads are cached at higher priority and writes bypass the cache. v1: (Ken) - Set caching policy for buffer surfaces too Signed-off-by: Sagar Ghuge Reviewed-by: Jason Ekstrand Part-of: --- src/intel/isl/isl_surface_state.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index 8ff98ffa14a..4129356e039 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -376,6 +376,11 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, s.MipTailStartLOD = 15; #endif +#if GFX_VERx10 >= 125 + /* Setting L1 caching policy to Write-back mode. */ + s.L1CacheControl = L1CC_WB; +#endif + #if GFX_VER >= 6 const struct isl_extent3d image_align = isl_get_image_alignment(info->surf); @@ -912,6 +917,11 @@ isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state, s.MOCS = info->mocs; #endif +#if GFX_VERx10 >= 125 + /* Setting L1 caching policy to Write-back mode. */ + s.L1CacheControl = L1CC_WB; +#endif + #if (GFX_VERx10 >= 75) s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->swizzle.r; s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->swizzle.g;