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radv: disable CPU caching for IBS to reduce fetch latency

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AMDGPU_GEM_CREATE_CPU_GTT_USWC should be faster when CPU reads
are unexpected (because they aren't cached).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5959>
This commit is contained in:
Samuel Pitoiset 2020-07-17 22:51:34 +02:00 • committed by Marge Bot
parent d2a3ca289f
commit d1bba2eee7
2 changed files with 6 additions and 3 deletions
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3
src/amd/vulkan/si_cmd_buffer.c
View file

@ -530,7 +530,8 @@ cik_create_gfx_config(struct radv_device *device)
RADEON_DOMAIN_GTT,
RADEON_FLAG_CPU_ACCESS|
RADEON_FLAG_NO_INTERPROCESS_SHARING |
RADEON_FLAG_READ_ONLY,
RADEON_FLAG_READ_ONLY |
RADEON_FLAG_GTT_WC,
RADV_BO_PRIORITY_CS);
if (!device->gfx_init)
goto fail;

6
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
View file

@ -324,7 +324,8 @@ radv_amdgpu_cs_create(struct radeon_winsys *ws,
RADEON_DOMAIN_GTT,
RADEON_FLAG_CPU_ACCESS |
RADEON_FLAG_NO_INTERPROCESS_SHARING |
RADEON_FLAG_READ_ONLY,
RADEON_FLAG_READ_ONLY |
RADEON_FLAG_GTT_WC,
RADV_BO_PRIORITY_CS);
if (!cs->ib_buffer) {
free(cs);
@ -440,7 +441,8 @@ static void radv_amdgpu_cs_grow(struct radeon_cmdbuf *_cs, size_t min_size)
RADEON_DOMAIN_GTT,
RADEON_FLAG_CPU_ACCESS |
RADEON_FLAG_NO_INTERPROCESS_SHARING |
RADEON_FLAG_READ_ONLY,
RADEON_FLAG_READ_ONLY |
RADEON_FLAG_GTT_WC,
RADV_BO_PRIORITY_CS);
if (!cs->ib_buffer) {