fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-22 09:10:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

intel/vec4: Remove inline lowering of LRP

Browse source 
Since dd7135d55d ("intel/compiler: Use the flrp lowering pass for all
stages on Gen4 and Gen5"), it's not possible to get to this function on
GPUs that don't have a LRP instruction.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6826>
This commit is contained in:
Ian Romanick 2020-09-22 12:46:05 -07:00
parent 86bab92aa4
commit d0ce24c8ca
1 changed files with 5 additions and 17 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

22
src/intel/compiler/brw_vec4_builder.h
View file

@ -501,23 +501,11 @@ namespace brw {
LRP(const dst_reg &dst, const src_reg &x, const src_reg &y, LRP(const dst_reg &dst, const src_reg &x, const src_reg &y,
const src_reg &a) const const src_reg &a) const
{ {
if (shader->devinfo->gen >= 6 && shader->devinfo->gen <= 10) { /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
/* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so * we need to reorder the operands.
* we need to reorder the operands. */
*/ assert(shader->devinfo->gen >= 6 && shader->devinfo->gen <= 9);
return emit(BRW_OPCODE_LRP, dst, a, y, x); return emit(BRW_OPCODE_LRP, dst, a, y, x);
} else {
/* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
const dst_reg y_times_a = vgrf(dst.type);
const dst_reg one_minus_a = vgrf(dst.type);
const dst_reg x_times_one_minus_a = vgrf(dst.type);
MUL(y_times_a, y, a);
ADD(one_minus_a, negate(a), brw_imm_f(1.0f));
MUL(x_times_one_minus_a, x, src_reg(one_minus_a));
return ADD(dst, src_reg(x_times_one_minus_a), src_reg(y_times_a));
}
} }
backend_shader *shader; backend_shader *shader;