From d0ce24c8caa14db94e6f6c1f6e1c0da5f58ca1e8 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 22 Sep 2020 12:46:05 -0700 Subject: [PATCH] intel/vec4: Remove inline lowering of LRP Since dd7135d55d5 ("intel/compiler: Use the flrp lowering pass for all stages on Gen4 and Gen5"), it's not possible to get to this function on GPUs that don't have a LRP instruction. Reviewed-by: Jason Ekstrand Reviewed-by: Matt Turner Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw_vec4_builder.h | 22 +++++----------------- 1 file changed, 5 insertions(+), 17 deletions(-) diff --git a/src/intel/compiler/brw_vec4_builder.h b/src/intel/compiler/brw_vec4_builder.h index 5c880c19f52..f056fe6a331 100644 --- a/src/intel/compiler/brw_vec4_builder.h +++ b/src/intel/compiler/brw_vec4_builder.h @@ -501,23 +501,11 @@ namespace brw { LRP(const dst_reg &dst, const src_reg &x, const src_reg &y, const src_reg &a) const { - if (shader->devinfo->gen >= 6 && shader->devinfo->gen <= 10) { - /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so - * we need to reorder the operands. - */ - return emit(BRW_OPCODE_LRP, dst, a, y, x); - - } else { - /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */ - const dst_reg y_times_a = vgrf(dst.type); - const dst_reg one_minus_a = vgrf(dst.type); - const dst_reg x_times_one_minus_a = vgrf(dst.type); - - MUL(y_times_a, y, a); - ADD(one_minus_a, negate(a), brw_imm_f(1.0f)); - MUL(x_times_one_minus_a, x, src_reg(one_minus_a)); - return ADD(dst, src_reg(x_times_one_minus_a), src_reg(y_times_a)); - } + /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so + * we need to reorder the operands. + */ + assert(shader->devinfo->gen >= 6 && shader->devinfo->gen <= 9); + return emit(BRW_OPCODE_LRP, dst, a, y, x); } backend_shader *shader;