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radv: do not use the whole HTILE buffer for depth when VRS is used

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The stencil data needs to be included for storing the VRS rates
into the HTILE buffer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10187>
This commit is contained in:
Samuel Pitoiset 2021-04-09 13:26:30 +02:00 • committed by Marge Bot
parent 73dac68cb8
commit d075711b0e
1 changed files with 1 additions and 1 deletions
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2
src/amd/vulkan/radv_private.h
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@ -1958,7 +1958,7 @@ static inline bool
radv_image_tile_stencil_disabled(const struct radv_device *device, const struct radv_image *image)
{
if (device->physical_device->rad_info.chip_class >= GFX9) {
return !vk_format_has_stencil(image->vk_format);
return !vk_format_has_stencil(image->vk_format) && !radv_image_has_vrs_htile(device, image);
} else {
/* Due to a hw bug, TILE_STENCIL_DISABLE must be set to 0 for
* the TC-compat ZRANGE issue even if no stencil is used.