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radv: configure the VRS HTILE encoding size
Any depth buffer can potentially use VRS. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10187>
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2 changed files with 15 additions and 0 deletions
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@ -6629,6 +6629,10 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf
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if (device->physical_device->rad_info.chip_class == GFX9) {
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ds->db_htile_surface |= S_028ABC_RB_ALIGNED(1);
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}
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if (radv_image_has_vrs_htile(device, iview->image)) {
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ds->db_htile_surface |= S_028ABC_VRS_HTILE_ENCODING(V_028ABC_VRS_HTILE_4BIT_ENCODING);
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}
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}
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} else {
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const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
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@ -1920,6 +1920,17 @@ radv_image_has_htile(const struct radv_image *image)
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image->planes[0].surface.meta_size;
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}
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/**
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* Return whether the image has VRS HTILE metadata for depth surfaces
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*/
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static inline bool
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radv_image_has_vrs_htile(const struct radv_device *device, const struct radv_image *image)
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{
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/* Any depth buffer can potentially use VRS. */
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return device->attachment_vrs_enabled && radv_image_has_htile(image) &&
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(image->usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT);
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}
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/**
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* Return whether HTILE metadata is enabled for a level.
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*/
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