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all: rename PIPE_SHADER_VERTEX to MESA_SHADER_VERTEX

Browse source 
Use command:
  find . -type f -not -path '*/.git/*' -exec sed -i 's/PIPE_SHADER_VERTEX/MESA_SHADER_VERTEX/g' {} +

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36569>
This commit is contained in:
Qiang Yu 2025-08-05 12:13:03 +08:00
parent c12497f943
commit cff8674fb4
170 changed files with 502 additions and 502 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/asahi/vulkan/hk_cmd_buffer.c
View file

@ -649,7 +649,7 @@ hk_reserve_scratch(struct hk_cmd_buffer *cmd, struct hk_cs *cs,
cs->scratch.fs.main = true;
cs->scratch.fs.preamble = MAX2(cs->scratch.fs.preamble, preamble_size);
break;
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
cs->scratch.vs.main = true;
cs->scratch.vs.preamble = MAX2(cs->scratch.vs.preamble, preamble_size);
break;

2
src/asahi/vulkan/hk_device.h
View file

@ -144,7 +144,7 @@ hk_device_scratch_locked(struct hk_device *dev, enum pipe_shader_type stage)
switch (stage) {
case PIPE_SHADER_FRAGMENT:
return &dev->scratch.fs;
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
return &dev->scratch.vs;
default:
return &dev->scratch.cs;

4
src/gallium/auxiliary/cso_cache/cso_context.c
View file

@ -422,7 +422,7 @@ cso_unbind_context(struct cso_context *cso)
ctx->base.pipe->bind_fs_state(ctx->base.pipe, NULL);
ctx->base.pipe->set_constant_buffer(ctx->base.pipe, PIPE_SHADER_FRAGMENT, 0, false, NULL);
ctx->base.pipe->bind_vs_state(ctx->base.pipe, NULL);
ctx->base.pipe->set_constant_buffer(ctx->base.pipe, PIPE_SHADER_VERTEX, 0, false, NULL);
ctx->base.pipe->set_constant_buffer(ctx->base.pipe, MESA_SHADER_VERTEX, 0, false, NULL);
if (ctx->has_geometry_shader) {
ctx->base.pipe->bind_gs_state(ctx->base.pipe, NULL);
}
@ -1750,7 +1750,7 @@ cso_restore_state(struct cso_context *ctx, unsigned unbind)
if (state_mask & CSO_BIT_VIEWPORT)
cso_restore_viewport(cso);
if (unbind & CSO_UNBIND_VS_CONSTANTS)
cso->base.pipe->set_constant_buffer(cso->base.pipe, PIPE_SHADER_VERTEX, 0, false, NULL);
cso->base.pipe->set_constant_buffer(cso->base.pipe, MESA_SHADER_VERTEX, 0, false, NULL);
if (unbind & CSO_UNBIND_FS_CONSTANTS)
cso->base.pipe->set_constant_buffer(cso->base.pipe, PIPE_SHADER_FRAGMENT, 0, false, NULL);
if (state_mask & CSO_BIT_VERTEX_ELEMENTS)

10
src/gallium/auxiliary/draw/draw_context.c
View file

@ -459,7 +459,7 @@ draw_set_mapped_constant_buffer(struct draw_context *draw,
const void *buffer,
unsigned size)
{
assert(shader_type == PIPE_SHADER_VERTEX ||
assert(shader_type == MESA_SHADER_VERTEX ||
shader_type == PIPE_SHADER_GEOMETRY ||
shader_type == PIPE_SHADER_TESS_CTRL ||
shader_type == PIPE_SHADER_TESS_EVAL);
@ -478,7 +478,7 @@ draw_set_mapped_shader_buffer(struct draw_context *draw,
const void *buffer,
unsigned size)
{
assert(shader_type == PIPE_SHADER_VERTEX ||
assert(shader_type == MESA_SHADER_VERTEX ||
shader_type == PIPE_SHADER_GEOMETRY ||
shader_type == PIPE_SHADER_TESS_CTRL ||
shader_type == PIPE_SHADER_TESS_EVAL);
@ -760,7 +760,7 @@ draw_texture_sampler(struct draw_context *draw,
struct tgsi_sampler *sampler)
{
switch (shader) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
draw->vs.tgsi.sampler = sampler;
break;
case PIPE_SHADER_GEOMETRY:
@ -784,7 +784,7 @@ draw_image(struct draw_context *draw,
struct tgsi_image *image)
{
switch (shader) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
draw->vs.tgsi.image = image;
break;
case PIPE_SHADER_GEOMETRY:
@ -808,7 +808,7 @@ draw_buffer(struct draw_context *draw,
struct tgsi_buffer *buffer)
{
switch (shader) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
draw->vs.tgsi.buffer = buffer;
break;
case PIPE_SHADER_GEOMETRY:

6
src/gallium/auxiliary/draw/draw_llvm.c
View file

@ -2095,11 +2095,11 @@ draw_llvm_make_variant_key(struct draw_llvm *llvm, char *store)
for (unsigned i = 0 ; i < key->nr_samplers; i++) {
lp_sampler_static_sampler_state(&draw_sampler[i].sampler_state,
llvm->draw->samplers[PIPE_SHADER_VERTEX][i]);
llvm->draw->samplers[MESA_SHADER_VERTEX][i]);
}
for (unsigned i = 0 ; i < key->nr_sampler_views; i++) {
lp_sampler_static_texture_state(&draw_sampler[i].texture_state,
llvm->draw->sampler_views[PIPE_SHADER_VERTEX][i]);
llvm->draw->sampler_views[MESA_SHADER_VERTEX][i]);
}
draw_image = draw_llvm_variant_key_images(key);
@ -2107,7 +2107,7 @@ draw_llvm_make_variant_key(struct draw_llvm *llvm, char *store)
key->nr_images * sizeof *draw_image);
for (unsigned i = 0; i < key->nr_images; i++) {
lp_sampler_static_texture_state_image(&draw_image[i].image_state,
llvm->draw->images[PIPE_SHADER_VERTEX][i]);
llvm->draw->images[MESA_SHADER_VERTEX][i]);
}
return key;
}

2
src/gallium/auxiliary/draw/draw_pt_fetch_shade_pipeline.c
View file

@ -270,7 +270,7 @@ fetch_pipeline_generic(struct draw_pt_middle_end *middle,
*/
if (fpme->opt & PT_SHADE) {
draw_vertex_shader_run(vshader,
draw->pt.user.constants[PIPE_SHADER_VERTEX],
draw->pt.user.constants[MESA_SHADER_VERTEX],
fetch_info,
vert_info,
&vs_vert_info);

4
src/gallium/auxiliary/draw/draw_pt_fetch_shade_pipeline_llvm.c
View file

@ -431,7 +431,7 @@ llvm_middle_end_bind_parameters(struct draw_pt_middle_end *middle)
struct draw_llvm *llvm = fpme->llvm;
unsigned i;
for (enum pipe_shader_type shader_type = PIPE_SHADER_VERTEX; shader_type <= PIPE_SHADER_GEOMETRY; shader_type++) {
for (enum pipe_shader_type shader_type = MESA_SHADER_VERTEX; shader_type <= PIPE_SHADER_GEOMETRY; shader_type++) {
for (i = 0; i < ARRAY_SIZE(llvm->jit_resources[shader_type].constants); ++i) {
/*
* There could be a potential issue with rounding this up, as the
@ -554,7 +554,7 @@ llvm_pipeline_generic(struct draw_pt_middle_end *middle,
}
/* Run vertex fetch shader */
clipped = fpme->current_variant->jit_func(&fpme->llvm->vs_jit_context,
&fpme->llvm->jit_resources[PIPE_SHADER_VERTEX],
&fpme->llvm->jit_resources[MESA_SHADER_VERTEX],
llvm_vert_info.verts,
draw->pt.user.vbuffer,
fetch_info->count,

4
src/gallium/auxiliary/draw/draw_vs.c
View file

@ -70,7 +70,7 @@ draw_create_vertex_shader(struct draw_context *draw,
if (draw->pt.middle.llvm) {
struct pipe_screen *screen = draw->pipe->screen;
if (shader->type == PIPE_SHADER_IR_NIR &&
!screen->shader_caps[PIPE_SHADER_VERTEX].integers) {
!screen->shader_caps[MESA_SHADER_VERTEX].integers) {
state.type = PIPE_SHADER_IR_TGSI;
state.tokens = nir_to_tgsi(shader->ir.nir, screen);
is_allocated = true;
@ -163,7 +163,7 @@ draw_vs_init(struct draw_context *draw)
draw->dump_vs = debug_get_option_gallium_dump_vs();
if (!draw->llvm) {
draw->vs.tgsi.machine = tgsi_exec_machine_create(PIPE_SHADER_VERTEX);
draw->vs.tgsi.machine = tgsi_exec_machine_create(MESA_SHADER_VERTEX);
if (!draw->vs.tgsi.machine)
return false;
}

4
src/gallium/auxiliary/draw/draw_vs_variant.c
View file

@ -175,7 +175,7 @@ vsvg_run_elts(struct draw_vs_variant *variant,
vsvg->base.vs->run_linear(vsvg->base.vs,
temp_buffer,
temp_buffer,
vsvg->base.vs->draw->pt.user.constants[PIPE_SHADER_VERTEX],
vsvg->base.vs->draw->pt.user.constants[MESA_SHADER_VERTEX],
count,
temp_vertex_stride,
temp_vertex_stride, NULL);
@ -238,7 +238,7 @@ vsvg_run_linear(struct draw_vs_variant *variant,
vsvg->base.vs->run_linear(vsvg->base.vs,
temp_buffer,
temp_buffer,
vsvg->base.vs->draw->pt.user.constants[PIPE_SHADER_VERTEX],
vsvg->base.vs->draw->pt.user.constants[MESA_SHADER_VERTEX],
count,
temp_vertex_stride,
temp_vertex_stride, NULL);

6
src/gallium/auxiliary/driver_ddebug/dd_draw.c
View file

@ -159,8 +159,8 @@ dd_num_active_viewports(struct dd_draw_state *dstate)
tokens = dstate->shaders[PIPE_SHADER_GEOMETRY]->state.shader.tokens;
else if (dstate->shaders[PIPE_SHADER_TESS_EVAL])
tokens = dstate->shaders[PIPE_SHADER_TESS_EVAL]->state.shader.tokens;
else if (dstate->shaders[PIPE_SHADER_VERTEX])
tokens = dstate->shaders[PIPE_SHADER_VERTEX]->state.shader.tokens;
else if (dstate->shaders[MESA_SHADER_VERTEX])
tokens = dstate->shaders[MESA_SHADER_VERTEX]->state.shader.tokens;
else
return 1;
@ -264,7 +264,7 @@ dd_dump_shader(struct dd_draw_state *dstate, enum pipe_shader_type sh, FILE *f)
int i;
const char *shader_str[PIPE_SHADER_TYPES];
shader_str[PIPE_SHADER_VERTEX] = "VERTEX";
shader_str[MESA_SHADER_VERTEX] = "VERTEX";
shader_str[PIPE_SHADER_TESS_CTRL] = "TESS_CTRL";
shader_str[PIPE_SHADER_TESS_EVAL] = "TESS_EVAL";
shader_str[PIPE_SHADER_GEOMETRY] = "GEOMETRY";

8
src/gallium/auxiliary/hud/hud_context.c
View file

@ -106,7 +106,7 @@ hud_draw_colored_prims(struct hud_context *hud, unsigned prim,
hud->constants.translate[1] = (float) (yoffset * hud_scale);
hud->constants.scale[0] = hud_scale;
hud->constants.scale[1] = yscale * hud_scale;
pipe->set_constant_buffer(pipe, PIPE_SHADER_VERTEX, 0, false, &hud->constbuf);
pipe->set_constant_buffer(pipe, MESA_SHADER_VERTEX, 0, false, &hud->constbuf);
u_upload_data(hud->pipe->stream_uploader, 0,
num_vertices * 2 * sizeof(float), 16, buffer,
@ -580,7 +580,7 @@ hud_draw_results(struct hud_context *hud, struct pipe_resource *tex)
pipe->set_sampler_views(pipe, PIPE_SHADER_FRAGMENT, 0, 1, 0,
&hud->font_sampler_view);
cso_set_samplers(cso, PIPE_SHADER_FRAGMENT, 1, sampler_states);
pipe->set_constant_buffer(pipe, PIPE_SHADER_VERTEX, 0, false, &hud->constbuf);
pipe->set_constant_buffer(pipe, MESA_SHADER_VERTEX, 0, false, &hud->constbuf);
/* draw accumulated vertices for background quads */
cso_set_blend(cso, &hud->alpha_blend);
@ -596,7 +596,7 @@ hud_draw_results(struct hud_context *hud, struct pipe_resource *tex)
hud->constants.scale[0] = hud_scale;
hud->constants.scale[1] = hud_scale;
pipe->set_constant_buffer(pipe, PIPE_SHADER_VERTEX, 0, false, &hud->constbuf);
pipe->set_constant_buffer(pipe, MESA_SHADER_VERTEX, 0, false, &hud->constbuf);
cso_set_vertex_buffers(cso, 1, true, &hud->bg.vbuf);
cso_draw_arrays(cso, MESA_PRIM_QUADS, 0, hud->bg.num_vertices);
@ -632,7 +632,7 @@ hud_draw_results(struct hud_context *hud, struct pipe_resource *tex)
hud->constants.translate[1] = 0;
hud->constants.scale[0] = hud_scale;
hud->constants.scale[1] = hud_scale;
pipe->set_constant_buffer(pipe, PIPE_SHADER_VERTEX, 0, false, &hud->constbuf);
pipe->set_constant_buffer(pipe, MESA_SHADER_VERTEX, 0, false, &hud->constbuf);
if (hud->whitelines.num_vertices) {
cso_set_vertex_shader_handle(cso, hud->vs_color);

2
src/gallium/auxiliary/postprocess/pp_mlaa.c
View file

@ -104,7 +104,7 @@ pp_jimenezmlaa_run(struct pp_queue_t *ppq, struct pipe_resource *in,
cb.user_buffer = constants;
struct pipe_context *pipe = ppq->p->pipe;
pipe->set_constant_buffer(pipe, PIPE_SHADER_VERTEX, 0, false, &cb);
pipe->set_constant_buffer(pipe, MESA_SHADER_VERTEX, 0, false, &cb);
pipe->set_constant_buffer(pipe, PIPE_SHADER_FRAGMENT, 0, false, &cb);
mstencil.stencil[0].enabled = 1;

2
src/gallium/auxiliary/tgsi/tgsi_from_mesa.h
View file

@ -61,7 +61,7 @@ tgsi_get_interp_mode(enum glsl_interp_mode mode, bool color);
static inline enum pipe_shader_type
pipe_shader_type_from_mesa(gl_shader_stage stage)
{
STATIC_ASSERT((enum pipe_shader_type) MESA_SHADER_VERTEX == PIPE_SHADER_VERTEX);
STATIC_ASSERT((enum pipe_shader_type) MESA_SHADER_VERTEX == MESA_SHADER_VERTEX);
STATIC_ASSERT((enum pipe_shader_type) MESA_SHADER_FRAGMENT == PIPE_SHADER_FRAGMENT);
STATIC_ASSERT((enum pipe_shader_type) MESA_SHADER_TESS_CTRL == PIPE_SHADER_TESS_CTRL);
STATIC_ASSERT((enum pipe_shader_type) MESA_SHADER_TESS_EVAL == PIPE_SHADER_TESS_EVAL);

2
src/gallium/auxiliary/tgsi/tgsi_scan.c
View file

@ -611,7 +611,7 @@ tgsi_scan_shader(const struct tgsi_token *tokens,
}
procType = parse.FullHeader.Processor.Processor;
assert(procType == PIPE_SHADER_FRAGMENT ||
procType == PIPE_SHADER_VERTEX ||
procType == MESA_SHADER_VERTEX ||
procType == PIPE_SHADER_GEOMETRY ||
procType == PIPE_SHADER_TESS_CTRL ||
procType == PIPE_SHADER_TESS_EVAL ||

4
src/gallium/auxiliary/tgsi/tgsi_text.c
View file

@ -335,7 +335,7 @@ static bool parse_header( struct translate_ctx *ctx )
if (str_match_nocase_whole( &ctx->cur, "FRAG" ))
processor = PIPE_SHADER_FRAGMENT;
else if (str_match_nocase_whole( &ctx->cur, "VERT" ))
processor = PIPE_SHADER_VERTEX;
processor = MESA_SHADER_VERTEX;
else if (str_match_nocase_whole( &ctx->cur, "GEOM" ))
processor = PIPE_SHADER_GEOMETRY;
else if (str_match_nocase_whole( &ctx->cur, "TESS_CTRL" ))
@ -1273,7 +1273,7 @@ static bool parse_declaration( struct translate_ctx *ctx )
}
is_vs_input = (file == TGSI_FILE_INPUT &&
ctx->processor == PIPE_SHADER_VERTEX);
ctx->processor == MESA_SHADER_VERTEX);
cur = ctx->cur;
eat_opt_white( &cur );

8
src/gallium/auxiliary/tgsi/tgsi_ureg.c
View file

@ -357,7 +357,7 @@ struct ureg_src
ureg_DECL_vs_input( struct ureg_program *ureg,
unsigned index )
{
assert(ureg->processor == PIPE_SHADER_VERTEX);
assert(ureg->processor == MESA_SHADER_VERTEX);
assert(index / 32 < ARRAY_SIZE(ureg->vs_inputs));
ureg->vs_inputs[index/32] |= 1 << (index % 32);
@ -1856,7 +1856,7 @@ static void emit_decls( struct ureg_program *ureg )
*/
qsort(ureg->input, ureg->nr_inputs, sizeof(ureg->input[0]), input_sort);
if (ureg->processor == PIPE_SHADER_VERTEX) {
if (ureg->processor == MESA_SHADER_VERTEX) {
for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
if (ureg->vs_inputs[i/32] & (1u << (i%32))) {
emit_decl_range( ureg, TGSI_FILE_INPUT, i, 1 );
@ -2113,7 +2113,7 @@ const struct tgsi_token *ureg_finalize( struct ureg_program *ureg )
const struct tgsi_token *tokens;
switch (ureg->processor) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
case PIPE_SHADER_TESS_EVAL:
ureg_property(ureg, TGSI_PROPERTY_NEXT_SHADER,
ureg->next_shader_processor == -1 ?
@ -2182,7 +2182,7 @@ void *ureg_create_shader( struct ureg_program *ureg,
state.stream_output = *so;
switch (ureg->processor) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
return pipe->create_vs_state(pipe, &state);
case PIPE_SHADER_TESS_CTRL:
return pipe->create_tcs_state(pipe, &state);

2
src/gallium/auxiliary/util/u_live_shader_cache.c
View file

@ -102,7 +102,7 @@ util_live_shader_cache_get(struct pipe_context *ctx,
unsigned char sha1[20];
_mesa_sha1_init(&sha1_ctx);
_mesa_sha1_update(&sha1_ctx, ir_binary, ir_size);
if ((stage == PIPE_SHADER_VERTEX ||
if ((stage == MESA_SHADER_VERTEX ||
stage == PIPE_SHADER_TESS_EVAL ||
stage == PIPE_SHADER_GEOMETRY) &&
state->stream_output.num_outputs) {

2
src/gallium/auxiliary/util/u_simple_shaders.c
View file

@ -80,7 +80,7 @@ util_make_vertex_passthrough_shader_with_so(struct pipe_context *pipe,
struct ureg_program *ureg;
unsigned i;
ureg = ureg_create( PIPE_SHADER_VERTEX );
ureg = ureg_create( MESA_SHADER_VERTEX );
if (!ureg)
return NULL;

6
src/gallium/auxiliary/util/u_threaded_context.c
View file

@ -910,7 +910,7 @@ tc_add_all_gfx_bindings_to_buffer_list(struct threaded_context *tc)
if (tc->seen_streamout_buffers)
tc_add_bindings_to_buffer_list(buffer_list, tc->streamout_buffers, PIPE_MAX_SO_BUFFERS);
tc_add_shader_bindings_to_buffer_list(tc, buffer_list, PIPE_SHADER_VERTEX);
tc_add_shader_bindings_to_buffer_list(tc, buffer_list, MESA_SHADER_VERTEX);
tc_add_shader_bindings_to_buffer_list(tc, buffer_list, PIPE_SHADER_FRAGMENT);
if (tc->seen_tcs)
@ -954,7 +954,7 @@ tc_rebind_buffer(struct threaded_context *tc, uint32_t old_id, uint32_t new_id,
}
unsigned rebound = vbo + so;
rebound += tc_rebind_shader_bindings(tc, old_id, new_id, PIPE_SHADER_VERTEX, rebind_mask);
rebound += tc_rebind_shader_bindings(tc, old_id, new_id, MESA_SHADER_VERTEX, rebind_mask);
rebound += tc_rebind_shader_bindings(tc, old_id, new_id, PIPE_SHADER_FRAGMENT, rebind_mask);
if (tc->seen_tcs)
@ -1006,7 +1006,7 @@ tc_is_buffer_bound_for_write(struct threaded_context *tc, uint32_t id)
BITFIELD_MASK(PIPE_MAX_SO_BUFFERS)))
return true;
if (tc_is_buffer_shader_bound_for_write(tc, id, PIPE_SHADER_VERTEX) ||
if (tc_is_buffer_shader_bound_for_write(tc, id, MESA_SHADER_VERTEX) ||
tc_is_buffer_shader_bound_for_write(tc, id, PIPE_SHADER_FRAGMENT) ||
tc_is_buffer_shader_bound_for_write(tc, id, PIPE_SHADER_COMPUTE))
return true;

2
src/gallium/auxiliary/vl/vl_bicubic_filter.c
View file

@ -54,7 +54,7 @@ create_vert_shader(struct vl_bicubic_filter *filter)
struct ureg_src i_vpos;
struct ureg_dst o_vpos, o_vtex;
shader = ureg_create(PIPE_SHADER_VERTEX);
shader = ureg_create(MESA_SHADER_VERTEX);
if (!shader)
return NULL;

2
src/gallium/auxiliary/vl/vl_compositor_gfx.c
View file

@ -60,7 +60,7 @@ create_vert_shader(struct vl_compositor *c)
struct ureg_dst o_vpos, o_vtex, o_color;
struct ureg_dst o_vtop, o_vbottom;
shader = ureg_create(PIPE_SHADER_VERTEX);
shader = ureg_create(MESA_SHADER_VERTEX);
if (!shader)
return NULL;

2
src/gallium/auxiliary/vl/vl_deint_filter.c
View file

@ -68,7 +68,7 @@ create_vert_shader(struct vl_deint_filter *filter)
struct ureg_src i_vpos;
struct ureg_dst o_vpos, o_vtex;
shader = ureg_create(PIPE_SHADER_VERTEX);
shader = ureg_create(MESA_SHADER_VERTEX);
if (!shader)
return NULL;

4
src/gallium/auxiliary/vl/vl_idct.c
View file

@ -148,7 +148,7 @@ create_mismatch_vert_shader(struct vl_idct *idct)
struct ureg_dst t_tex;
struct ureg_dst o_vpos, o_addr[2];
shader = ureg_create(PIPE_SHADER_VERTEX);
shader = ureg_create(MESA_SHADER_VERTEX);
if (!shader)
return NULL;
@ -264,7 +264,7 @@ create_stage1_vert_shader(struct vl_idct *idct)
struct ureg_dst t_tex, t_start;
struct ureg_dst o_vpos, o_l_addr[2], o_r_addr[2];
shader = ureg_create(PIPE_SHADER_VERTEX);
shader = ureg_create(MESA_SHADER_VERTEX);
if (!shader)
return NULL;

2
src/gallium/auxiliary/vl/vl_matrix_filter.c
View file

@ -52,7 +52,7 @@ create_vert_shader(struct vl_matrix_filter *filter)
struct ureg_src i_vpos;
struct ureg_dst o_vpos, o_vtex;
shader = ureg_create(PIPE_SHADER_VERTEX);
shader = ureg_create(MESA_SHADER_VERTEX);
if (!shader)
return NULL;

4
src/gallium/auxiliary/vl/vl_mc.c
View file

@ -112,7 +112,7 @@ create_ref_vert_shader(struct vl_mc *r)
struct ureg_dst o_vmv[2];
unsigned i;
shader = ureg_create(PIPE_SHADER_VERTEX);
shader = ureg_create(MESA_SHADER_VERTEX);
if (!shader)
return NULL;
@ -241,7 +241,7 @@ create_ycbcr_vert_shader(struct vl_mc *r, vl_mc_ycbcr_vert_shader vs_callback, v
unsigned label;
shader = ureg_create(PIPE_SHADER_VERTEX);
shader = ureg_create(MESA_SHADER_VERTEX);
if (!shader)
return NULL;

2
src/gallium/auxiliary/vl/vl_median_filter.c
View file

@ -50,7 +50,7 @@ create_vert_shader(struct vl_median_filter *filter)
struct ureg_src i_vpos;
struct ureg_dst o_vpos, o_vtex;
shader = ureg_create(PIPE_SHADER_VERTEX);
shader = ureg_create(MESA_SHADER_VERTEX);
if (!shader)
return NULL;

2
src/gallium/auxiliary/vl/vl_zscan.c
View file

@ -60,7 +60,7 @@ create_vert_shader(struct vl_zscan *zscan)
struct ureg_dst *o_vtex;
unsigned i;
shader = ureg_create(PIPE_SHADER_VERTEX);
shader = ureg_create(MESA_SHADER_VERTEX);
if (!shader)
return NULL;

2
src/gallium/drivers/asahi/agx_blit.c
View file

@ -459,7 +459,7 @@ agx_blitter_save(struct agx_context *ctx, struct blitter_context *blitter,
enum asahi_blitter_op op)
{
util_blitter_save_vertex_shader(blitter,
ctx->stage[PIPE_SHADER_VERTEX].shader);
ctx->stage[MESA_SHADER_VERTEX].shader);
util_blitter_save_tessctrl_shader(blitter,
ctx->stage[PIPE_SHADER_TESS_CTRL].shader);
util_blitter_save_tesseval_shader(blitter,

4
src/gallium/drivers/asahi/agx_disk_cache.c
View file

@ -34,7 +34,7 @@ agx_disk_cache_compute_key(struct disk_cache *cache,
uint8_t data[sizeof(uncompiled->nir_sha1) + sizeof(*shader_key)];
int hash_size = sizeof(uncompiled->nir_sha1);
int key_size;
if (uncompiled->type == PIPE_SHADER_VERTEX ||
if (uncompiled->type == MESA_SHADER_VERTEX ||
uncompiled->type == PIPE_SHADER_TESS_EVAL)
key_size = sizeof(shader_key->vs);
else if (uncompiled->type == PIPE_SHADER_FRAGMENT)
@ -93,7 +93,7 @@ read_shader(struct agx_screen *screen, struct blob_reader *blob,
blob_copy_bytes(blob, &binary->b.info, sizeof(binary->b.info));
size_t size = binary->b.info.binary_size;
if (uncompiled->type == PIPE_SHADER_VERTEX ||
if (uncompiled->type == MESA_SHADER_VERTEX ||
uncompiled->type == PIPE_SHADER_TESS_EVAL ||
uncompiled->type == PIPE_SHADER_FRAGMENT) {

2
src/gallium/drivers/asahi/agx_nir_lower_sysvals.c
View file

@ -381,7 +381,7 @@ lay_out_uniforms(struct agx_compiled_shader *shader, struct state *state)
{
unsigned uniform = 0;
if (state->stage == PIPE_SHADER_VERTEX ||
if (state->stage == MESA_SHADER_VERTEX ||
state->stage == PIPE_SHADER_TESS_EVAL) {
unsigned count =
DIV_ROUND_UP(BITSET_LAST_BIT(shader->attrib_components_read), 4);

4
src/gallium/drivers/asahi/agx_pipe.c
View file

@ -1873,14 +1873,14 @@ agx_init_shader_caps(struct pipe_screen *pscreen)
caps->max_control_flow_depth = 1024;
caps->max_inputs = i == PIPE_SHADER_VERTEX ? 16 : 32;
caps->max_inputs = i == MESA_SHADER_VERTEX ? 16 : 32;
/* For vertex, the spec min/max is 16. We need more to handle dmat3
* correctly, though. The full 32 is undesirable since it would require
* shenanigans to handle.
*/
caps->max_outputs = i == PIPE_SHADER_FRAGMENT ? 8
: i == PIPE_SHADER_VERTEX ? 24
: i == MESA_SHADER_VERTEX ? 24
: 32;
caps->max_temps = 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */

30
src/gallium/drivers/asahi/agx_state.c
View file

@ -431,7 +431,7 @@ agx_bind_rasterizer_state(struct pipe_context *pctx, void *cso)
static bool
has_edgeflags(struct agx_context *ctx, enum mesa_prim mode)
{
return ctx->stage[PIPE_SHADER_VERTEX].shader->info.has_edgeflags &&
return ctx->stage[MESA_SHADER_VERTEX].shader->info.has_edgeflags &&
mode == MESA_PRIM_TRIANGLES &&
(ctx->rast->base.fill_front != PIPE_POLYGON_MODE_FILL);
}
@ -1716,7 +1716,7 @@ agx_get_shader_variant(struct agx_screen *screen, struct pipe_context *pctx,
if (so->type == PIPE_SHADER_FRAGMENT) {
memcpy(cloned_key, key, sizeof(struct asahi_fs_shader_key));
} else if (so->type == PIPE_SHADER_VERTEX ||
} else if (so->type == MESA_SHADER_VERTEX ||
so->type == PIPE_SHADER_TESS_EVAL) {
memcpy(cloned_key, key, sizeof(struct asahi_vs_shader_key));
} else {
@ -1952,7 +1952,7 @@ agx_create_shader_state(struct pipe_context *pctx,
(so->type == PIPE_SHADER_FRAGMENT && !so->info.uses_fbfetch)) {
union asahi_shader_key key = {0};
agx_get_shader_variant(agx_screen(pctx->screen), pctx, so, &key);
} else if (so->type == PIPE_SHADER_VERTEX) {
} else if (so->type == MESA_SHADER_VERTEX) {
union asahi_shader_key key = {
.vs.hw = next_stage == MESA_SHADER_FRAGMENT,
};
@ -2173,7 +2173,7 @@ agx_update_vs(struct agx_batch *batch, unsigned index_size_B)
ctx->stage[PIPE_SHADER_GEOMETRY].shader),
};
agx_update_shader(ctx, &ctx->vs, PIPE_SHADER_VERTEX,
agx_update_shader(ctx, &ctx->vs, MESA_SHADER_VERTEX,
(union asahi_shader_key *)&key);
struct agx_device *dev = agx_device(ctx->base.screen);
@ -2199,7 +2199,7 @@ agx_update_vs(struct agx_batch *batch, unsigned index_size_B)
void *old = ctx->linked.vs;
ctx->linked.vs =
asahi_fast_link(ctx, ctx->stage[PIPE_SHADER_VERTEX].shader, &link_key);
asahi_fast_link(ctx, ctx->stage[MESA_SHADER_VERTEX].shader, &link_key);
agx_batch_add_bo(batch, ctx->vs->bo);
if (ctx->linked.vs)
@ -2396,7 +2396,7 @@ agx_bind_shader_state(struct pipe_context *pctx, void *cso,
{
struct agx_context *ctx = agx_context(pctx);
if (stage == PIPE_SHADER_VERTEX)
if (stage == MESA_SHADER_VERTEX)
ctx->dirty |= AGX_DIRTY_VS_PROG;
else if (stage == PIPE_SHADER_FRAGMENT)
ctx->dirty |= AGX_DIRTY_FS_PROG;
@ -2409,7 +2409,7 @@ agx_bind_shader_state(struct pipe_context *pctx, void *cso,
static void
agx_bind_vs_state(struct pipe_context *pctx, void *cso)
{
agx_bind_shader_state(pctx, cso, PIPE_SHADER_VERTEX);
agx_bind_shader_state(pctx, cso, MESA_SHADER_VERTEX);
}
static void
@ -2961,7 +2961,7 @@ agx_build_pipeline(struct agx_batch *batch, struct agx_compiled_shader *cs,
batch->fs_preamble_scratch =
MAX2(batch->fs_preamble_scratch, preamble_size);
break;
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
agx_scratch_alloc(&ctx->scratch_vs, max_scratch_size, max_subgroups);
batch->vs_scratch = true;
batch->vs_preamble_scratch =
@ -3494,7 +3494,7 @@ agx_encode_state(struct agx_batch *batch, uint8_t *out)
agx_push(out, VDM_STATE_VERTEX_SHADER_WORD_1, cfg) {
cfg.pipeline =
agx_build_pipeline(batch, vs, ctx->gs ? NULL : ctx->linked.vs,
PIPE_SHADER_VERTEX, 0, 0);
MESA_SHADER_VERTEX, 0, 0);
}
agx_push_packed(out, vs->uvs.vdm, VDM_STATE_VERTEX_OUTPUTS);
@ -4309,7 +4309,7 @@ agx_needs_passthrough_gs(struct agx_context *ctx,
*/
struct agx_uncompiled_shader *last_vtx =
ctx->stage[PIPE_SHADER_TESS_EVAL].shader
?: ctx->stage[PIPE_SHADER_VERTEX].shader;
?: ctx->stage[MESA_SHADER_VERTEX].shader;
if (last_vtx->has_xfb_info && ctx->streamout.num_targets) {
*xfb_only = true;
@ -4385,7 +4385,7 @@ agx_apply_passthrough_gs(struct agx_context *ctx,
{
enum pipe_shader_type prev_stage = ctx->stage[PIPE_SHADER_TESS_EVAL].shader
? PIPE_SHADER_TESS_EVAL
: PIPE_SHADER_VERTEX;
: MESA_SHADER_VERTEX;
struct agx_uncompiled_shader *prev_cso = ctx->stage[prev_stage].shader;
assert(ctx->stage[PIPE_SHADER_GEOMETRY].shader == NULL);
@ -4688,7 +4688,7 @@ agx_draw_patches(struct agx_context *ctx, const struct pipe_draw_info *info,
batch->uniforms.tess_params = state;
agx_launch(batch, vs_grid, agx_workgroup(64, 1, 1), ctx->vs, ctx->linked.vs,
PIPE_SHADER_VERTEX, 0);
MESA_SHADER_VERTEX, 0);
agx_launch(batch, tcs_grid, agx_workgroup(tcs->tess.output_patch_size, 1, 1),
ctx->tcs, NULL, PIPE_SHADER_TESS_CTRL, 0);
@ -4720,7 +4720,7 @@ agx_draw_patches(struct agx_context *ctx, const struct pipe_draw_info *info,
ctx->dirty |= AGX_DIRTY_RS;
/* Run TES as VS */
void *vs_cso = ctx->stage[PIPE_SHADER_VERTEX].shader;
void *vs_cso = ctx->stage[MESA_SHADER_VERTEX].shader;
void *tes_cso = ctx->stage[PIPE_SHADER_TESS_EVAL].shader;
ctx->base.bind_vs_state(&ctx->base, tes_cso);
ctx->in_tess = true;
@ -5013,8 +5013,8 @@ agx_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info,
/* Update shaders first so we can use them after */
if (agx_update_vs(batch, info->index_size)) {
ctx->dirty |= AGX_DIRTY_VS | AGX_DIRTY_VS_PROG;
ctx->stage[PIPE_SHADER_VERTEX].dirty = ~0;
} else if (ctx->stage[PIPE_SHADER_VERTEX].dirty ||
ctx->stage[MESA_SHADER_VERTEX].dirty = ~0;
} else if (ctx->stage[MESA_SHADER_VERTEX].dirty ||
(ctx->dirty & AGX_DIRTY_VERTEX))
ctx->dirty |= AGX_DIRTY_VS;

2
src/gallium/drivers/asahi/agx_state.h
View file

@ -88,7 +88,7 @@ enum agx_sysval_table {
#define AGX_SYSVAL_STAGE(stage) (AGX_SYSVAL_TABLE_VS + (stage))
static_assert(AGX_SYSVAL_STAGE(PIPE_SHADER_VERTEX) == AGX_SYSVAL_TABLE_VS,
static_assert(AGX_SYSVAL_STAGE(MESA_SHADER_VERTEX) == AGX_SYSVAL_TABLE_VS,
"fixed enum orderings");
static_assert(AGX_SYSVAL_STAGE(PIPE_SHADER_TESS_CTRL) == AGX_SYSVAL_TABLE_TCS,
"fixed enum orderings");

4
src/gallium/drivers/crocus/crocus_screen.c
View file

@ -144,12 +144,12 @@ crocus_init_shader_caps(struct crocus_screen *screen)
(struct pipe_shader_caps *)&screen->base.shader_caps[i];
if (devinfo->ver < 6 &&
i != PIPE_SHADER_VERTEX &&
i != MESA_SHADER_VERTEX &&
i != PIPE_SHADER_FRAGMENT)
continue;
if (devinfo->ver == 6 &&
i != PIPE_SHADER_VERTEX &&
i != MESA_SHADER_VERTEX &&
i != PIPE_SHADER_FRAGMENT &&
i != PIPE_SHADER_GEOMETRY)
continue;

2
src/gallium/drivers/crocus/crocus_state.c
View file

@ -2320,7 +2320,7 @@ crocus_bind_sampler_states(struct pipe_context *ctx,
#if GFX_VER <= 5
if (p_stage == PIPE_SHADER_FRAGMENT)
ice->state.dirty |= CROCUS_DIRTY_WM;
else if (p_stage == PIPE_SHADER_VERTEX)
else if (p_stage == MESA_SHADER_VERTEX)
ice->state.stage_dirty |= CROCUS_STAGE_DIRTY_VS;
#endif
ice->state.stage_dirty |= CROCUS_STAGE_DIRTY_SAMPLER_STATES_VS << stage;

2
src/gallium/drivers/d3d12/d3d12_blit.cpp
View file

@ -271,7 +271,7 @@ util_blit_save_state(struct d3d12_context *ctx)
util_blitter_save_stencil_ref(ctx->blitter, &ctx->stencil_ref);
util_blitter_save_rasterizer(ctx->blitter, ctx->gfx_pipeline_state.rast);
util_blitter_save_fragment_shader(ctx->blitter, ctx->gfx_stages[PIPE_SHADER_FRAGMENT]);
util_blitter_save_vertex_shader(ctx->blitter, ctx->gfx_stages[PIPE_SHADER_VERTEX]);
util_blitter_save_vertex_shader(ctx->blitter, ctx->gfx_stages[MESA_SHADER_VERTEX]);
util_blitter_save_geometry_shader(ctx->blitter, ctx->gfx_stages[PIPE_SHADER_GEOMETRY]);
util_blitter_save_tessctrl_shader(ctx->blitter, ctx->gfx_stages[PIPE_SHADER_TESS_CTRL]);
util_blitter_save_tesseval_shader(ctx->blitter, ctx->gfx_stages[PIPE_SHADER_TESS_EVAL]);

34
src/gallium/drivers/d3d12/d3d12_compiler.cpp
View file

@ -104,7 +104,7 @@ compile_nir(struct d3d12_context *ctx, struct d3d12_shader_selector *sel,
key->n_texture_states, key->tex_wrap_states, key->swizzle_state,
screen->base.caps.max_texture_lod_bias);
if (key->stage == PIPE_SHADER_VERTEX && key->vs.needs_format_emulation)
if (key->stage == MESA_SHADER_VERTEX && key->vs.needs_format_emulation)
dxil_nir_lower_vs_vertex_conversion(nir, key->vs.format_conversion);
if (key->last_vertex_processing_stage) {
@ -325,7 +325,7 @@ needs_edge_flag_fix(enum mesa_prim mode)
static unsigned
fill_mode_lowered(struct d3d12_context *ctx, const struct pipe_draw_info *dinfo)
{
struct d3d12_shader_selector *vs = ctx->gfx_stages[PIPE_SHADER_VERTEX];
struct d3d12_shader_selector *vs = ctx->gfx_stages[MESA_SHADER_VERTEX];
if ((ctx->gfx_stages[PIPE_SHADER_GEOMETRY] != NULL &&
!ctx->gfx_stages[PIPE_SHADER_GEOMETRY]->is_variant) ||
@ -365,7 +365,7 @@ has_stream_out_for_streams(struct d3d12_context *ctx)
static bool
needs_point_sprite_lowering(struct d3d12_context *ctx, const struct pipe_draw_info *dinfo)
{
struct d3d12_shader_selector *vs = ctx->gfx_stages[PIPE_SHADER_VERTEX];
struct d3d12_shader_selector *vs = ctx->gfx_stages[MESA_SHADER_VERTEX];
struct d3d12_shader_selector *gs = ctx->gfx_stages[PIPE_SHADER_GEOMETRY];
if (gs != NULL && !gs->is_variant) {
@ -407,7 +407,7 @@ get_provoking_vertex(struct d3d12_selection_context *sel_ctx, bool *alternate, c
return 0;
}
struct d3d12_shader_selector *vs = sel_ctx->ctx->gfx_stages[PIPE_SHADER_VERTEX];
struct d3d12_shader_selector *vs = sel_ctx->ctx->gfx_stages[MESA_SHADER_VERTEX];
struct d3d12_shader_selector *gs = sel_ctx->ctx->gfx_stages[PIPE_SHADER_GEOMETRY];
struct d3d12_shader_selector *last_vertex_stage = gs && !gs->is_variant ? gs : vs;
@ -416,7 +416,7 @@ get_provoking_vertex(struct d3d12_selection_context *sel_ctx, bool *alternate, c
case PIPE_SHADER_GEOMETRY:
mode = (enum mesa_prim)last_vertex_stage->initial->info.gs.output_primitive;
break;
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
mode = (enum mesa_prim)dinfo->mode;
break;
default:
@ -630,7 +630,7 @@ validate_geometry_shader_variant(struct d3d12_selection_context *sel_ctx)
if (gs != NULL && !gs->is_variant)
return;
d3d12_shader_selector* vs = ctx->gfx_stages[PIPE_SHADER_VERTEX];
d3d12_shader_selector* vs = ctx->gfx_stages[MESA_SHADER_VERTEX];
d3d12_shader_selector* fs = ctx->gfx_stages[PIPE_SHADER_FRAGMENT];
struct d3d12_gs_variant_key key;
@ -707,7 +707,7 @@ d3d12_compare_shader_keys(struct d3d12_selection_context* sel_ctx, const d3d12_s
return false;
switch (expect->stage) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
if (expect->vs.needs_format_emulation != have->vs.needs_format_emulation)
return false;
@ -800,7 +800,7 @@ d3d12_shader_key_hash(const d3d12_shader_key *key)
if (key->prev_has_frac_outputs)
hash = _mesa_hash_data_with_seed(key->prev_varying_frac_outputs, sizeof(d3d12_shader_selector::varying_frac_outputs), hash);
switch (key->stage) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
/* (Probably) not worth the bit extraction for needs_format_emulation and
* the rest of the the format_conversion data is large. Don't bother
* hashing for now until this is shown to be worthwhile. */
@ -843,7 +843,7 @@ d3d12_fill_shader_key(struct d3d12_selection_context *sel_ctx,
switch (stage)
{
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
key->vs.needs_format_emulation = 0;
break;
case PIPE_SHADER_FRAGMENT:
@ -903,7 +903,7 @@ d3d12_fill_shader_key(struct d3d12_selection_context *sel_ctx,
}
if (stage == PIPE_SHADER_GEOMETRY ||
((stage == PIPE_SHADER_VERTEX || stage == PIPE_SHADER_TESS_EVAL) &&
((stage == MESA_SHADER_VERTEX || stage == PIPE_SHADER_TESS_EVAL) &&
(!next || next->stage == PIPE_SHADER_FRAGMENT))) {
key->last_vertex_processing_stage = 1;
key->invert_depth = sel_ctx->ctx->reverse_depth_range;
@ -1015,7 +1015,7 @@ d3d12_fill_shader_key(struct d3d12_selection_context *sel_ctx,
memset(key->tex_wrap_states, 0, sizeof(key->tex_wrap_states[0]) * key->n_texture_states);
}
if (stage == PIPE_SHADER_VERTEX && sel_ctx->ctx->gfx_pipeline_state.ves) {
if (stage == MESA_SHADER_VERTEX && sel_ctx->ctx->gfx_pipeline_state.ves) {
key->vs.needs_format_emulation = sel_ctx->ctx->gfx_pipeline_state.ves->needs_format_emulation;
if (key->vs.needs_format_emulation) {
unsigned num_elements = sel_ctx->ctx->gfx_pipeline_state.ves->num_elements;
@ -1200,7 +1200,7 @@ static d3d12_shader_selector *
get_prev_shader(struct d3d12_context *ctx, pipe_shader_type current)
{
switch (current) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
return NULL;
case PIPE_SHADER_FRAGMENT:
if (ctx->gfx_stages[PIPE_SHADER_GEOMETRY])
@ -1215,7 +1215,7 @@ get_prev_shader(struct d3d12_context *ctx, pipe_shader_type current)
return ctx->gfx_stages[PIPE_SHADER_TESS_CTRL];
FALLTHROUGH;
case PIPE_SHADER_TESS_CTRL:
return ctx->gfx_stages[PIPE_SHADER_VERTEX];
return ctx->gfx_stages[MESA_SHADER_VERTEX];
default:
UNREACHABLE("shader type not supported");
}
@ -1225,7 +1225,7 @@ static d3d12_shader_selector *
get_next_shader(struct d3d12_context *ctx, pipe_shader_type current)
{
switch (current) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
if (ctx->gfx_stages[PIPE_SHADER_TESS_CTRL])
return ctx->gfx_stages[PIPE_SHADER_TESS_CTRL];
FALLTHROUGH;
@ -1509,9 +1509,9 @@ d3d12_select_shader_variants(struct d3d12_context *ctx, const struct pipe_draw_i
auto* stages = ctx->gfx_stages;
d3d12_shader_selector* prev;
d3d12_shader_selector* next;
if (stages[PIPE_SHADER_VERTEX]) {
next = get_next_shader(ctx, PIPE_SHADER_VERTEX);
select_shader_variant(&sel_ctx, stages[PIPE_SHADER_VERTEX], nullptr, next);
if (stages[MESA_SHADER_VERTEX]) {
next = get_next_shader(ctx, MESA_SHADER_VERTEX);
select_shader_variant(&sel_ctx, stages[MESA_SHADER_VERTEX], nullptr, next);
}
if (stages[PIPE_SHADER_TESS_CTRL]) {
prev = get_prev_shader(ctx, PIPE_SHADER_TESS_CTRL);

8
src/gallium/drivers/d3d12/d3d12_context_graphics.cpp
View file

@ -1074,14 +1074,14 @@ static void *
d3d12_create_vs_state(struct pipe_context *pctx,
const struct pipe_shader_state *shader)
{
return d3d12_create_shader(d3d12_context(pctx), PIPE_SHADER_VERTEX, shader);
return d3d12_create_shader(d3d12_context(pctx), MESA_SHADER_VERTEX, shader);
}
static void
d3d12_bind_vs_state(struct pipe_context *pctx,
void *vss)
{
bind_stage(d3d12_context(pctx), PIPE_SHADER_VERTEX,
bind_stage(d3d12_context(pctx), MESA_SHADER_VERTEX,
(struct d3d12_shader_selector *) vss);
}
@ -1089,7 +1089,7 @@ static void
d3d12_delete_vs_state(struct pipe_context *pctx,
void *vs)
{
delete_shader(d3d12_context(pctx), PIPE_SHADER_VERTEX,
delete_shader(d3d12_context(pctx), MESA_SHADER_VERTEX,
(struct d3d12_shader_selector *) vs);
}
@ -1951,7 +1951,7 @@ d3d12_clear_render_target(struct pipe_context *pctx,
util_blitter_save_stencil_ref(ctx->blitter, &ctx->stencil_ref);
util_blitter_save_rasterizer(ctx->blitter, ctx->gfx_pipeline_state.rast);
util_blitter_save_fragment_shader(ctx->blitter, ctx->gfx_stages[PIPE_SHADER_FRAGMENT]);
util_blitter_save_vertex_shader(ctx->blitter, ctx->gfx_stages[PIPE_SHADER_VERTEX]);
util_blitter_save_vertex_shader(ctx->blitter, ctx->gfx_stages[MESA_SHADER_VERTEX]);
util_blitter_save_geometry_shader(ctx->blitter, ctx->gfx_stages[PIPE_SHADER_GEOMETRY]);
util_blitter_save_tessctrl_shader(ctx->blitter, ctx->gfx_stages[PIPE_SHADER_TESS_CTRL]);
util_blitter_save_tesseval_shader(ctx->blitter, ctx->gfx_stages[PIPE_SHADER_TESS_EVAL]);

8
src/gallium/drivers/d3d12/d3d12_draw.cpp
View file

@ -747,7 +747,7 @@ d3d12_last_vertex_stage(struct d3d12_context *ctx)
if (!sel || sel->is_variant)
sel = ctx->gfx_stages[PIPE_SHADER_TESS_EVAL];
if (!sel)
sel = ctx->gfx_stages[PIPE_SHADER_VERTEX];
sel = ctx->gfx_stages[MESA_SHADER_VERTEX];
return sel;
}
@ -759,10 +759,10 @@ update_draw_indirect_with_sysvals(struct d3d12_context *ctx,
struct pipe_draw_indirect_info *indirect_out)
{
if (*indirect_inout == nullptr ||
ctx->gfx_stages[PIPE_SHADER_VERTEX] == nullptr)
ctx->gfx_stages[MESA_SHADER_VERTEX] == nullptr)
return false;
auto sys_values_read = ctx->gfx_stages[PIPE_SHADER_VERTEX]->initial->info.system_values_read;
auto sys_values_read = ctx->gfx_stages[MESA_SHADER_VERTEX]->initial->info.system_values_read;
bool any = BITSET_TEST(sys_values_read, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) ||
BITSET_TEST(sys_values_read, SYSTEM_VALUE_BASE_VERTEX) ||
BITSET_TEST(sys_values_read, SYSTEM_VALUE_FIRST_VERTEX) ||
@ -839,7 +839,7 @@ update_draw_auto(struct d3d12_context *ctx,
{
if (*indirect_inout == nullptr ||
(*indirect_inout)->count_from_stream_output == nullptr ||
ctx->gfx_stages[PIPE_SHADER_VERTEX] == nullptr)
ctx->gfx_stages[MESA_SHADER_VERTEX] == nullptr)
return false;
d3d12_compute_transform_save_restore save;

6
src/gallium/drivers/d3d12/d3d12_pipeline_state.cpp
View file

@ -283,8 +283,8 @@ create_gfx_pipeline_state(struct d3d12_context *ctx)
nir_shader *last_vertex_stage_nir = NULL;
if (state->stages[PIPE_SHADER_VERTEX]) {
auto shader = state->stages[PIPE_SHADER_VERTEX];
if (state->stages[MESA_SHADER_VERTEX]) {
auto shader = state->stages[MESA_SHADER_VERTEX];
pso_desc.VS = D3D12_SHADER_BYTECODE { shader->bytecode, shader->bytecode_length };
last_vertex_stage_nir = shader->nir;
}
@ -347,7 +347,7 @@ create_gfx_pipeline_state(struct d3d12_context *ctx)
D3D12_INPUT_LAYOUT_DESC& input_layout = (D3D12_INPUT_LAYOUT_DESC&)pso_desc.InputLayout;
input_layout.pInputElementDescs = state->ves->elements;
input_layout.NumElements = state->ves->num_elements;
copy_input_attribs(state->ves->elements, input_attribs, &input_layout, state->stages[PIPE_SHADER_VERTEX]->nir);
copy_input_attribs(state->ves->elements, input_attribs, &input_layout, state->stages[MESA_SHADER_VERTEX]->nir);
pso_desc.IBStripCutValue = state->ib_strip_cut_value;

2
src/gallium/drivers/d3d12/d3d12_root_signature.cpp
View file

@ -41,7 +41,7 @@ static D3D12_SHADER_VISIBILITY
get_shader_visibility(enum pipe_shader_type stage)
{
switch (stage) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
return D3D12_SHADER_VISIBILITY_VERTEX;
case PIPE_SHADER_FRAGMENT:
return D3D12_SHADER_VISIBILITY_PIXEL;

2
src/gallium/drivers/d3d12/d3d12_screen.cpp
View file

@ -138,7 +138,7 @@ d3d12_init_shader_caps(struct d3d12_screen *screen)
caps->max_control_flow_depth = INT_MAX;
switch (i) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
caps->max_inputs = D3D12_VS_INPUT_REGISTER_COUNT;
caps->max_outputs = D3D12_VS_OUTPUT_REGISTER_COUNT;
break;

4
src/gallium/drivers/etnaviv/etnaviv_context.c
View file

@ -343,8 +343,8 @@ etna_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info,
if (ctx->dirty & ETNA_DIRTY_SHADER) {
/* Mark constant buffers as being read */
u_foreach_bit(i, ctx->constant_buffer[PIPE_SHADER_VERTEX].enabled_mask)
resource_read(ctx, ctx->constant_buffer[PIPE_SHADER_VERTEX].cb[i].buffer);
u_foreach_bit(i, ctx->constant_buffer[MESA_SHADER_VERTEX].enabled_mask)
resource_read(ctx, ctx->constant_buffer[MESA_SHADER_VERTEX].cb[i].buffer);
u_foreach_bit(i, ctx->constant_buffer[PIPE_SHADER_FRAGMENT].enabled_mask)
resource_read(ctx, ctx->constant_buffer[PIPE_SHADER_FRAGMENT].cb[i].buffer);

4
src/gallium/drivers/etnaviv/etnaviv_emit.c
View file

@ -744,7 +744,7 @@ etna_emit_state(struct etna_context *ctx)
if (need_steering)
etna_set_state(stream, VIVS_SH_CONTROL, 0x0);
etna_uniforms_write(ctx, ctx->shader.vs, ctx->constant_buffer[PIPE_SHADER_VERTEX].cb);
etna_uniforms_write(ctx, ctx->shader.vs, ctx->constant_buffer[MESA_SHADER_VERTEX].cb);
if (need_steering)
etna_set_state(stream, VIVS_SH_CONTROL, VIVS_SH_CONTROL_PS_UNIFORM);
@ -763,7 +763,7 @@ etna_emit_state(struct etna_context *ctx)
etna_set_state(stream, VIVS_SH_CONTROL, 0x0);
if (dirty & (uniform_dirty_bits | ctx->shader.vs->uniforms_dirty_bits))
etna_uniforms_write(ctx, ctx->shader.vs, ctx->constant_buffer[PIPE_SHADER_VERTEX].cb);
etna_uniforms_write(ctx, ctx->shader.vs, ctx->constant_buffer[MESA_SHADER_VERTEX].cb);
/* ideally this cache would only be flushed if there are PS uniform changes */
if (need_steering)

2
src/gallium/drivers/etnaviv/etnaviv_screen.c
View file

@ -201,7 +201,7 @@ etna_init_single_shader_caps(struct etna_screen *screen, enum pipe_shader_type s
static void
etna_init_shader_caps(struct etna_screen *screen)
{
etna_init_single_shader_caps(screen, PIPE_SHADER_VERTEX);
etna_init_single_shader_caps(screen, MESA_SHADER_VERTEX);
etna_init_single_shader_caps(screen, PIPE_SHADER_FRAGMENT);
}

4
src/gallium/drivers/etnaviv/etnaviv_texture.c
View file

@ -54,7 +54,7 @@ etna_bind_sampler_states(struct pipe_context *pctx, enum pipe_shader_type shader
offset = 0;
ctx->num_fragment_samplers = num_samplers;
break;
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
offset = screen->specs.vertex_sampler_offset;
break;
default:
@ -334,7 +334,7 @@ etna_set_sampler_views(struct pipe_context *pctx, enum pipe_shader_type shader,
case PIPE_SHADER_FRAGMENT:
etna_fragtex_set_sampler_views(ctx, num_views, views);
break;
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
etna_vertex_set_sampler_views(ctx, num_views, views);
break;
default:;

2
src/gallium/drivers/freedreno/a2xx/fd2_draw.c
View file

@ -637,7 +637,7 @@ dirty:
FD_DIRTY_SAMPLE_MASK | FD_DIRTY_PROG | FD_DIRTY_CONST |
FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
ctx->dirty_shader[PIPE_SHADER_VERTEX] |= FD_DIRTY_SHADER_PROG;
ctx->dirty_shader[MESA_SHADER_VERTEX] |= FD_DIRTY_SHADER_PROG;
ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |=
FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_CONST;

6
src/gallium/drivers/freedreno/a2xx/fd2_emit.c
View file

@ -138,7 +138,7 @@ static void
emit_textures(struct fd_ringbuffer *ring, struct fd_context *ctx)
{
struct fd_texture_stateobj *fragtex = &ctx->tex[PIPE_SHADER_FRAGMENT];
struct fd_texture_stateobj *verttex = &ctx->tex[PIPE_SHADER_VERTEX];
struct fd_texture_stateobj *verttex = &ctx->tex[MESA_SHADER_VERTEX];
texmask emitted = 0;
unsigned i;
@ -180,7 +180,7 @@ fd2_emit_state_binning(struct fd_context *ctx,
if (dirty & (FD_DIRTY_PROG | FD_DIRTY_CONST)) {
emit_constants(ring, VS_CONST_BASE * 4,
&ctx->constbuf[PIPE_SHADER_VERTEX],
&ctx->constbuf[MESA_SHADER_VERTEX],
(dirty & FD_DIRTY_PROG) ? ctx->prog.vs : NULL);
}
@ -348,7 +348,7 @@ fd2_emit_state(struct fd_context *ctx, const enum fd_dirty_3d_state dirty)
if (dirty & (FD_DIRTY_PROG | FD_DIRTY_CONST)) {
emit_constants(ring, VS_CONST_BASE * 4,
&ctx->constbuf[PIPE_SHADER_VERTEX],
&ctx->constbuf[MESA_SHADER_VERTEX],
(dirty & FD_DIRTY_PROG) ? ctx->prog.vs : NULL);
emit_constants(ring, PS_CONST_BASE * 4,
&ctx->constbuf[PIPE_SHADER_FRAGMENT],

2
src/gallium/drivers/freedreno/a2xx/fd2_program.c
View file

@ -175,7 +175,7 @@ fd2_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
/* clear/gmem2mem/mem2gmem need to be changed to remove this condition */
if (prog != &ctx->solid_prog && prog != &ctx->blit_prog[0]) {
patch_fetches(ctx, vpi, ctx->vtx.vtx, &ctx->tex[PIPE_SHADER_VERTEX]);
patch_fetches(ctx, vpi, ctx->vtx.vtx, &ctx->tex[MESA_SHADER_VERTEX]);
if (fp)
patch_fetches(ctx, fpi, NULL, &ctx->tex[PIPE_SHADER_FRAGMENT]);
}

2
src/gallium/drivers/freedreno/a3xx/fd3_draw.c
View file

@ -42,7 +42,7 @@ draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
fd3_emit_state(ctx, ring, emit);
if ((ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_PROG) ||
if ((ctx->dirty_shader[MESA_SHADER_VERTEX] & FD_DIRTY_SHADER_PROG) ||
(emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE)))
fd3_emit_vertex_bufs(ring, emit);

4
src/gallium/drivers/freedreno/a3xx/fd3_emit.c
View file

@ -810,8 +810,8 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
if (dirty & FD_DIRTY_TEX)
fd_wfi(ctx->batch, ring);
if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX)
emit_textures(ctx, ring, SB_VERT_TEX, &ctx->tex[PIPE_SHADER_VERTEX]);
if (ctx->dirty_shader[MESA_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX)
emit_textures(ctx, ring, SB_VERT_TEX, &ctx->tex[MESA_SHADER_VERTEX]);
if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX)
emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->tex[PIPE_SHADER_FRAGMENT]);

2
src/gallium/drivers/freedreno/a4xx/fd4_draw.c
View file

@ -30,7 +30,7 @@ draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
fd4_emit_state(ctx, ring, emit);
if ((ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_PROG) ||
if ((ctx->dirty_shader[MESA_SHADER_VERTEX] & FD_DIRTY_SHADER_PROG) ||
(emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE)))
fd4_emit_vertex_bufs(ring, emit);

4
src/gallium/drivers/freedreno/a4xx/fd4_emit.c
View file

@ -894,8 +894,8 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_RING(ring, A4XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
}
if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX)
emit_textures(ctx, ring, SB4_VS_TEX, &ctx->tex[PIPE_SHADER_VERTEX], vp);
if (ctx->dirty_shader[MESA_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX)
emit_textures(ctx, ring, SB4_VS_TEX, &ctx->tex[MESA_SHADER_VERTEX], vp);
if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX)
emit_textures(ctx, ring, SB4_FS_TEX, &ctx->tex[PIPE_SHADER_FRAGMENT], fp);

4
src/gallium/drivers/freedreno/a4xx/fd4_texture.c
View file

@ -226,7 +226,7 @@ fd4_set_sampler_views(struct pipe_context *pctx, enum pipe_shader_type shader,
if (shader == PIPE_SHADER_FRAGMENT) {
sampler_swizzles = fd4_ctx->fsampler_swizzles;
} else if (shader == PIPE_SHADER_VERTEX) {
} else if (shader == MESA_SHADER_VERTEX) {
sampler_swizzles = fd4_ctx->vsampler_swizzles;
} else if (shader == PIPE_SHADER_COMPUTE) {
sampler_swizzles = fd4_ctx->csampler_swizzles;
@ -276,7 +276,7 @@ fd4_set_sampler_views(struct pipe_context *pctx, enum pipe_shader_type shader,
if (shader == PIPE_SHADER_FRAGMENT) {
fd4_ctx->fastc_srgb = astc_srgb;
} else if (shader == PIPE_SHADER_VERTEX) {
} else if (shader == MESA_SHADER_VERTEX) {
fd4_ctx->vastc_srgb = astc_srgb;
} else if (shader == PIPE_SHADER_COMPUTE) {
fd4_ctx->castc_srgb = astc_srgb;

2
src/gallium/drivers/freedreno/a5xx/fd5_draw.c
View file

@ -30,7 +30,7 @@ draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
fd5_emit_state(ctx, ring, emit);
if ((ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_PROG) ||
if ((ctx->dirty_shader[MESA_SHADER_VERTEX] & FD_DIRTY_SHADER_PROG) ||
(emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE)))
fd5_emit_vertex_bufs(ring, emit);

12
src/gallium/drivers/freedreno/a5xx/fd5_emit.c
View file

@ -300,9 +300,9 @@ emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring) assert_dt
entries = ptr;
setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
setup_border_colors(&ctx->tex[MESA_SHADER_VERTEX], &entries[0]);
setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
&entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
&entries[ctx->tex[MESA_SHADER_VERTEX].num_samplers]);
OUT_PKT4(ring, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
OUT_RELOC(ring, fd_resource(fd5_ctx->border_color_buf)->bo, off, 0, 0);
@ -317,7 +317,7 @@ emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
{
bool needs_border = false;
unsigned bcolor_offset =
(sb == SB4_FS_TEX) ? ctx->tex[PIPE_SHADER_VERTEX].num_samplers : 0;
(sb == SB4_FS_TEX) ? ctx->tex[MESA_SHADER_VERTEX].num_samplers : 0;
unsigned i;
if (tex->num_samplers > 0) {
@ -822,11 +822,11 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_RING(ring, A5XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
}
if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX) {
if (ctx->dirty_shader[MESA_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX) {
needs_border |=
emit_textures(ctx, ring, SB4_VS_TEX, &ctx->tex[PIPE_SHADER_VERTEX]);
emit_textures(ctx, ring, SB4_VS_TEX, &ctx->tex[MESA_SHADER_VERTEX]);
OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
OUT_RING(ring, ctx->tex[PIPE_SHADER_VERTEX].num_textures);
OUT_RING(ring, ctx->tex[MESA_SHADER_VERTEX].num_textures);
}
if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX) {

2
src/gallium/drivers/freedreno/a6xx/fd6_const.cc
View file

@ -347,7 +347,7 @@ fd6_build_user_consts(struct fd6_emit *emit)
struct fd_ringbuffer *constobj =
fd_submit_new_ringbuffer(ctx->batch->submit, sz, FD_RINGBUFFER_STREAMING);
emit_user_consts<CHIP>(emit->vs, constobj, &ctx->constbuf[PIPE_SHADER_VERTEX]);
emit_user_consts<CHIP>(emit->vs, constobj, &ctx->constbuf[MESA_SHADER_VERTEX]);
if (PIPELINE == HAS_TESS_GS) {
if (emit->hs) {

4
src/gallium/drivers/freedreno/a6xx/fd6_context.cc
View file

@ -177,7 +177,7 @@ setup_state_map(struct fd_context *ctx)
fd_context_add_map(ctx, FD_DIRTY_BLEND_COHERENT,
BIT(FD6_GROUP_PRIM_MODE_SYSMEM) | BIT(FD6_GROUP_PRIM_MODE_GMEM));
fd_context_add_shader_map(ctx, PIPE_SHADER_VERTEX, FD_DIRTY_SHADER_TEX,
fd_context_add_shader_map(ctx, MESA_SHADER_VERTEX, FD_DIRTY_SHADER_TEX,
BIT(FD6_GROUP_VS_TEX));
fd_context_add_shader_map(ctx, PIPE_SHADER_TESS_CTRL, FD_DIRTY_SHADER_TEX,
BIT(FD6_GROUP_HS_TEX));
@ -190,7 +190,7 @@ setup_state_map(struct fd_context *ctx)
fd_context_add_shader_map(ctx, PIPE_SHADER_COMPUTE, FD_DIRTY_SHADER_TEX,
BIT(FD6_GROUP_CS_TEX));
fd_context_add_shader_map(ctx, PIPE_SHADER_VERTEX,
fd_context_add_shader_map(ctx, MESA_SHADER_VERTEX,
FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE,
BIT(FD6_GROUP_VS_BINDLESS));
fd_context_add_shader_map(ctx, PIPE_SHADER_TESS_CTRL,

4
src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
View file

@ -659,7 +659,7 @@ fd6_emit_3d_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
fd6_state_take_group(&emit->state, state, FD6_GROUP_SAMPLE_LOCATIONS);
break;
case FD6_GROUP_VS_BINDLESS:
state = fd6_build_bindless_state<CHIP>(ctx, PIPE_SHADER_VERTEX, false);
state = fd6_build_bindless_state<CHIP>(ctx, MESA_SHADER_VERTEX, false);
fd6_state_take_group(&emit->state, state, FD6_GROUP_VS_BINDLESS);
break;
case FD6_GROUP_HS_BINDLESS:
@ -693,7 +693,7 @@ fd6_emit_3d_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
}
break;
case FD6_GROUP_VS_TEX:
state = tex_state(ctx, PIPE_SHADER_VERTEX);
state = tex_state(ctx, MESA_SHADER_VERTEX);
fd6_state_take_group(&emit->state, state, FD6_GROUP_VS_TEX);
break;
case FD6_GROUP_HS_TEX:

2
src/gallium/drivers/freedreno/a6xx/fd6_texture.cc
View file

@ -610,7 +610,7 @@ build_texture_state(struct fd_context *ctx, enum pipe_shader_type type,
enum a6xx_state_block sb;
switch (type) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
sb = SB6_VS_TEX;
opcode = CP_LOAD_STATE6_GEOM;
tex_samp_reg = REG_A6XX_SP_VS_SAMPLER_BASE;

6
src/gallium/drivers/freedreno/freedreno_program.c
View file

@ -72,8 +72,8 @@ fd_vs_state_bind(struct pipe_context *pctx, void *hwcso) in_dt
{
struct fd_context *ctx = fd_context(pctx);
ctx->prog.vs = hwcso;
fd_context_dirty_shader(ctx, PIPE_SHADER_VERTEX, FD_DIRTY_SHADER_PROG);
update_bound_stage(ctx, PIPE_SHADER_VERTEX, !!hwcso);
fd_context_dirty_shader(ctx, MESA_SHADER_VERTEX, FD_DIRTY_SHADER_PROG);
update_bound_stage(ctx, MESA_SHADER_VERTEX, !!hwcso);
}
static void
@ -160,7 +160,7 @@ fd_prog_blit_vs(struct pipe_context *pctx)
{
struct ureg_program *ureg;
ureg = ureg_create(PIPE_SHADER_VERTEX);
ureg = ureg_create(MESA_SHADER_VERTEX);
if (!ureg)
return NULL;

2
src/gallium/drivers/freedreno/freedreno_screen.c
View file

@ -271,7 +271,7 @@ fd_init_shader_caps(struct fd_screen *screen)
caps->supported_irs =
(1 << PIPE_SHADER_IR_NIR) |
/* tgsi_to_nir doesn't support all stages: */
COND(i == PIPE_SHADER_VERTEX ||
COND(i == MESA_SHADER_VERTEX ||
i == PIPE_SHADER_FRAGMENT ||
i == PIPE_SHADER_COMPUTE,
1 << PIPE_SHADER_IR_TGSI);

2
src/gallium/drivers/freedreno/ir3/ir3_const.h
View file

@ -568,7 +568,7 @@ ir3_emit_vs_consts(const struct ir3_shader_variant *v,
{
assert(v->type == MESA_SHADER_VERTEX);
emit_common_consts(v, ring, ctx, PIPE_SHADER_VERTEX);
emit_common_consts(v, ring, ctx, MESA_SHADER_VERTEX);
/* emit driver params every time: */
if (info && v->need_driver_params) {

2
src/gallium/drivers/freedreno/ir3/ir3_descriptor.h
View file

@ -35,7 +35,7 @@ static inline unsigned
ir3_shader_descriptor_set(enum pipe_shader_type shader)
{
switch (shader) {
case PIPE_SHADER_VERTEX: return 0;
case MESA_SHADER_VERTEX: return 0;
case PIPE_SHADER_TESS_CTRL: return 1;
case PIPE_SHADER_TESS_EVAL: return 2;
case PIPE_SHADER_GEOMETRY: return 3;

2
src/gallium/drivers/freedreno/ir3/ir3_gallium.c
View file

@ -469,7 +469,7 @@ ir3_fixup_shader_state(struct pipe_context *pctx, struct ir3_shader_key *key)
}
if (ir3_shader_key_changes_vs(ctx->last.key, key)) {
fd_context_dirty_shader(ctx, PIPE_SHADER_VERTEX, FD_DIRTY_SHADER_PROG);
fd_context_dirty_shader(ctx, MESA_SHADER_VERTEX, FD_DIRTY_SHADER_PROG);
}
/* NOTE: currently only a6xx has gs/tess, but needs no

10
src/gallium/drivers/i915/i915_context.c
View file

@ -100,14 +100,14 @@ i915_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info,
draw_set_indexes(draw, (uint8_t *)mapped_indices, info->index_size, ~0);
}
if (i915->constants[PIPE_SHADER_VERTEX])
if (i915->constants[MESA_SHADER_VERTEX])
draw_set_mapped_constant_buffer(
draw, PIPE_SHADER_VERTEX, 0,
i915_buffer(i915->constants[PIPE_SHADER_VERTEX])->data,
(i915->current.num_user_constants[PIPE_SHADER_VERTEX] * 4 *
draw, MESA_SHADER_VERTEX, 0,
i915_buffer(i915->constants[MESA_SHADER_VERTEX])->data,
(i915->current.num_user_constants[MESA_SHADER_VERTEX] * 4 *
sizeof(float)));
else
draw_set_mapped_constant_buffer(draw, PIPE_SHADER_VERTEX, 0, NULL, 0);
draw_set_mapped_constant_buffer(draw, MESA_SHADER_VERTEX, 0, NULL, 0);
/*
* Do the drawing

4
src/gallium/drivers/i915/i915_screen.c
View file

@ -254,7 +254,7 @@ static void
i915_init_shader_caps(struct i915_screen *is)
{
struct pipe_shader_caps *caps =
(struct pipe_shader_caps *)&is->base.shader_caps[PIPE_SHADER_VERTEX];
(struct pipe_shader_caps *)&is->base.shader_caps[MESA_SHADER_VERTEX];
draw_init_shader_caps(caps);
@ -557,7 +557,7 @@ i915_screen_create(struct i915_winsys *iws)
is->base.fence_reference = i915_fence_reference;
is->base.fence_finish = i915_fence_finish;
is->base.nir_options[PIPE_SHADER_VERTEX] = &gallivm_nir_options;
is->base.nir_options[MESA_SHADER_VERTEX] = &gallivm_nir_options;
is->base.nir_options[PIPE_SHADER_FRAGMENT] = &i915_compiler_options;
i915_init_screen_resource_functions(is);

2
src/gallium/drivers/i915/i915_state.c
View file

@ -770,7 +770,7 @@ i915_set_constant_buffer(struct pipe_context *pipe,
i915->current.num_user_constants[shader] = new_num;
if (diff)
i915->dirty |= shader == PIPE_SHADER_VERTEX ? I915_NEW_VS_CONSTANTS
i915->dirty |= shader == MESA_SHADER_VERTEX ? I915_NEW_VS_CONSTANTS
: I915_NEW_FS_CONSTANTS;
if (cb && cb->user_buffer) {

2
src/gallium/drivers/iris/iris_screen.c
View file

@ -212,7 +212,7 @@ iris_init_shader_caps(struct iris_screen *screen)
caps->max_control_flow_depth = UINT_MAX;
caps->max_inputs = i == PIPE_SHADER_VERTEX ? 16 : 32;
caps->max_inputs = i == MESA_SHADER_VERTEX ? 16 : 32;
caps->max_outputs = 32;
caps->max_const_buffer0_size = 16 * 1024 * sizeof(float);
caps->max_const_buffers = 16;

8
src/gallium/drivers/lima/lima_draw.c
View file

@ -289,7 +289,7 @@ lima_pack_vs_cmd(struct lima_context *ctx, const struct pipe_draw_info *info,
const struct pipe_draw_start_count_bias *draw)
{
struct lima_context_constant_buffer *ccb =
ctx->const_buffer + PIPE_SHADER_VERTEX;
ctx->const_buffer + MESA_SHADER_VERTEX;
struct lima_vs_compiled_shader *vs = ctx->vs;
struct lima_job *job = lima_job_get(ctx);
@ -820,7 +820,7 @@ static void
lima_update_gp_uniform(struct lima_context *ctx)
{
struct lima_context_constant_buffer *ccb =
ctx->const_buffer + PIPE_SHADER_VERTEX;
ctx->const_buffer + MESA_SHADER_VERTEX;
struct lima_vs_compiled_shader *vs = ctx->vs;
int uniform_size = MIN2(vs->state.uniform_size, ccb->size);
@ -1004,11 +1004,11 @@ lima_draw_vbo_update(struct pipe_context *pctx,
lima_update_gp_attribute_info(ctx, info, draw);
if ((ctx->dirty & LIMA_CONTEXT_DIRTY_CONST_BUFF &&
ctx->const_buffer[PIPE_SHADER_VERTEX].dirty) ||
ctx->const_buffer[MESA_SHADER_VERTEX].dirty) ||
ctx->dirty & LIMA_CONTEXT_DIRTY_VIEWPORT ||
ctx->dirty & LIMA_CONTEXT_DIRTY_COMPILED_VS) {
lima_update_gp_uniform(ctx);
ctx->const_buffer[PIPE_SHADER_VERTEX].dirty = false;
ctx->const_buffer[MESA_SHADER_VERTEX].dirty = false;
}
lima_update_varying(ctx, info, draw);

2
src/gallium/drivers/lima/lima_program.c
View file

@ -94,7 +94,7 @@ const void *
lima_program_get_compiler_options(enum pipe_shader_type shader)
{
switch (shader) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
return &vs_nir_options;
case PIPE_SHADER_FRAGMENT:
return &fs_nir_options;

2
src/gallium/drivers/lima/lima_screen.c
View file

@ -99,7 +99,7 @@ static void
lima_init_shader_caps(struct pipe_screen *screen)
{
struct pipe_shader_caps *caps =
(struct pipe_shader_caps *)&screen->shader_caps[PIPE_SHADER_VERTEX];
(struct pipe_shader_caps *)&screen->shader_caps[MESA_SHADER_VERTEX];
caps->max_instructions =
caps->max_alu_instructions =

2
src/gallium/drivers/llvmpipe/lp_context.c
View file

@ -84,7 +84,7 @@ llvmpipe_destroy(struct pipe_context *pipe)
util_unreference_framebuffer_state(&llvmpipe->framebuffer);
for (enum pipe_shader_type s = PIPE_SHADER_VERTEX; s < PIPE_SHADER_MESH_TYPES; s++) {
for (enum pipe_shader_type s = MESA_SHADER_VERTEX; s < PIPE_SHADER_MESH_TYPES; s++) {
for (i = 0; i < ARRAY_SIZE(llvmpipe->sampler_views[0]); i++) {
pipe_sampler_view_reference(&llvmpipe->sampler_views[s][i], NULL);
}

12
src/gallium/drivers/llvmpipe/lp_draw_arrays.c
View file

@ -107,8 +107,8 @@ llvmpipe_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info,
}
llvmpipe_prepare_vertex_sampling(lp,
lp->num_sampler_views[PIPE_SHADER_VERTEX],
lp->sampler_views[PIPE_SHADER_VERTEX]);
lp->num_sampler_views[MESA_SHADER_VERTEX],
lp->sampler_views[MESA_SHADER_VERTEX]);
llvmpipe_prepare_geometry_sampling(lp,
lp->num_sampler_views[PIPE_SHADER_GEOMETRY],
lp->sampler_views[PIPE_SHADER_GEOMETRY]);
@ -120,8 +120,8 @@ llvmpipe_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info,
lp->sampler_views[PIPE_SHADER_TESS_EVAL]);
llvmpipe_prepare_vertex_images(lp,
lp->num_images[PIPE_SHADER_VERTEX],
lp->images[PIPE_SHADER_VERTEX]);
lp->num_images[MESA_SHADER_VERTEX],
lp->images[MESA_SHADER_VERTEX]);
llvmpipe_prepare_geometry_images(lp,
lp->num_images[PIPE_SHADER_GEOMETRY],
lp->images[PIPE_SHADER_GEOMETRY]);
@ -168,12 +168,12 @@ llvmpipe_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info,
}
}
llvmpipe_cleanup_stage_sampling(lp, PIPE_SHADER_VERTEX);
llvmpipe_cleanup_stage_sampling(lp, MESA_SHADER_VERTEX);
llvmpipe_cleanup_stage_sampling(lp, PIPE_SHADER_GEOMETRY);
llvmpipe_cleanup_stage_sampling(lp, PIPE_SHADER_TESS_CTRL);
llvmpipe_cleanup_stage_sampling(lp, PIPE_SHADER_TESS_EVAL);
llvmpipe_cleanup_stage_images(lp, PIPE_SHADER_VERTEX);
llvmpipe_cleanup_stage_images(lp, MESA_SHADER_VERTEX);
llvmpipe_cleanup_stage_images(lp, PIPE_SHADER_GEOMETRY);
llvmpipe_cleanup_stage_images(lp, PIPE_SHADER_TESS_CTRL);
llvmpipe_cleanup_stage_images(lp, PIPE_SHADER_TESS_EVAL);

2
src/gallium/drivers/llvmpipe/lp_screen.c
View file

@ -135,7 +135,7 @@ llvmpipe_init_shader_caps(struct pipe_screen *screen)
break;
case PIPE_SHADER_TESS_CTRL:
case PIPE_SHADER_TESS_EVAL:
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
case PIPE_SHADER_GEOMETRY:
draw_init_shader_caps(caps);

6
src/gallium/drivers/llvmpipe/lp_state_fs.c
View file

@ -4244,7 +4244,7 @@ llvmpipe_set_constant_buffer(struct pipe_context *pipe,
}
switch (shader) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
case PIPE_SHADER_GEOMETRY:
case PIPE_SHADER_TESS_CTRL:
case PIPE_SHADER_TESS_EVAL: {
@ -4301,7 +4301,7 @@ llvmpipe_set_shader_buffers(struct pipe_context *pipe,
}
switch (shader) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
case PIPE_SHADER_GEOMETRY:
case PIPE_SHADER_TESS_CTRL:
case PIPE_SHADER_TESS_EVAL: {
@ -4361,7 +4361,7 @@ llvmpipe_set_shader_images(struct pipe_context *pipe,
llvmpipe->num_images[shader] = start_slot + count;
switch (shader) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
case PIPE_SHADER_GEOMETRY:
case PIPE_SHADER_TESS_CTRL:
case PIPE_SHADER_TESS_EVAL:

8
src/gallium/drivers/llvmpipe/lp_state_sampler.c
View file

@ -97,7 +97,7 @@ llvmpipe_bind_sampler_states(struct pipe_context *pipe,
}
switch (shader) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
case PIPE_SHADER_GEOMETRY:
case PIPE_SHADER_TESS_CTRL:
case PIPE_SHADER_TESS_EVAL:
@ -180,7 +180,7 @@ llvmpipe_set_sampler_views(struct pipe_context *pipe,
}
switch (shader) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
case PIPE_SHADER_GEOMETRY:
case PIPE_SHADER_TESS_CTRL:
case PIPE_SHADER_TESS_EVAL:
@ -390,7 +390,7 @@ llvmpipe_prepare_vertex_sampling(struct llvmpipe_context *lp,
unsigned num,
struct pipe_sampler_view **views)
{
prepare_shader_sampling(lp, num, views, PIPE_SHADER_VERTEX);
prepare_shader_sampling(lp, num, views, MESA_SHADER_VERTEX);
}
@ -549,7 +549,7 @@ llvmpipe_prepare_vertex_images(struct llvmpipe_context *lp,
unsigned num,
struct pipe_image_view *views)
{
prepare_shader_images(lp, num, views, PIPE_SHADER_VERTEX);
prepare_shader_images(lp, num, views, MESA_SHADER_VERTEX);
}

2
src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
View file

@ -979,7 +979,7 @@ nv50_ir_prog_info_out_print(struct nv50_ir_prog_info_out *info_out)
INFO(" \"prop\":{\n");
switch (info_out->type) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
INFO(" \"vp\": {\"usesDrawParameters\":\"%s\"}\n",
info_out->prop.vp.usesDrawParameters ? "true" : "false");
break;

4
src/gallium/drivers/nouveau/codegen/nv50_ir_serialize.cpp
View file

@ -109,7 +109,7 @@ nv50_ir_prog_info_out_serialize(struct blob *blob,
blob_write_bytes(blob, info_out->out, info_out->numOutputs * sizeof(info_out->out[0]));
switch(info_out->type) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
blob_write_bytes(blob, &info_out->prop.vp, sizeof(info_out->prop.vp));
break;
case PIPE_SHADER_TESS_CTRL:
@ -229,7 +229,7 @@ nv50_ir_prog_info_out_deserialize(void *data, size_t size, size_t offset,
blob_copy_bytes(&reader, info_out->out, info_out->numOutputs * sizeof(info_out->out[0]));
switch(info_out->type) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
blob_copy_bytes(&reader, &info_out->prop.vp, sizeof(info_out->prop.vp));
break;
case PIPE_SHADER_TESS_CTRL:

4
src/gallium/drivers/nouveau/nv30/nv30_draw.c
View file

@ -414,10 +414,10 @@ nv30_render_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info,
if (nv30->draw_dirty & NV30_NEW_VERTCONST) {
if (nv30->vertprog.constbuf) {
void *map = nv04_resource(nv30->vertprog.constbuf)->data;
draw_set_mapped_constant_buffer(draw, PIPE_SHADER_VERTEX, 0,
draw_set_mapped_constant_buffer(draw, MESA_SHADER_VERTEX, 0,
map, nv30->vertprog.constbuf_nr * 16);
} else {
draw_set_mapped_constant_buffer(draw, PIPE_SHADER_VERTEX, 0, NULL, 0);
draw_set_mapped_constant_buffer(draw, MESA_SHADER_VERTEX, 0, NULL, 0);
}
}

2
src/gallium/drivers/nouveau/nv30/nv30_fragtex.c
View file

@ -207,7 +207,7 @@ nv30_set_sampler_views(struct pipe_context *pipe, enum pipe_shader_type shader,
case PIPE_SHADER_FRAGMENT:
nv30_fragtex_set_sampler_views(pipe, nr, views);
break;
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
nv40_verttex_set_sampler_views(pipe, nr, views);
break;
default:

2
src/gallium/drivers/nouveau/nv30/nv30_screen.c
View file

@ -54,7 +54,7 @@ nv30_init_shader_caps(struct nv30_screen *screen)
struct nouveau_object *eng3d = screen->eng3d;
struct pipe_shader_caps *caps =
(struct pipe_shader_caps *)&screen->base.base.shader_caps[PIPE_SHADER_VERTEX];
(struct pipe_shader_caps *)&screen->base.base.shader_caps[MESA_SHADER_VERTEX];
caps->max_instructions =
caps->max_alu_instructions = (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;

2
src/gallium/drivers/nouveau/nv30/nv30_state.c
View file

@ -345,7 +345,7 @@ nv30_set_constant_buffer(struct pipe_context *pipe,
if (buf)
size = buf->width0 / (4 * sizeof(float));
if (shader == PIPE_SHADER_VERTEX) {
if (shader == MESA_SHADER_VERTEX) {
if (pass_reference) {
pipe_resource_reference(&nv30->vertprog.constbuf, NULL);
nv30->vertprog.constbuf = buf;

2
src/gallium/drivers/nouveau/nv30/nv30_texture.c
View file

@ -192,7 +192,7 @@ nv30_bind_sampler_states(struct pipe_context *pipe,
unsigned num_samplers, void **samplers)
{
switch (shader) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
nv40_verttex_sampler_states_bind(pipe, num_samplers, samplers);
break;
case PIPE_SHADER_FRAGMENT:

2
src/gallium/drivers/nouveau/nv50/nv50_context.h
View file

@ -247,7 +247,7 @@ static inline unsigned
nv50_context_shader_stage(unsigned pipe)
{
switch (pipe) {
case PIPE_SHADER_VERTEX: return NV50_SHADER_STAGE_VERTEX;
case MESA_SHADER_VERTEX: return NV50_SHADER_STAGE_VERTEX;
case PIPE_SHADER_FRAGMENT: return NV50_SHADER_STAGE_FRAGMENT;
case PIPE_SHADER_GEOMETRY: return NV50_SHADER_STAGE_GEOMETRY;
case PIPE_SHADER_COMPUTE: return NV50_SHADER_STAGE_COMPUTE;

6
src/gallium/drivers/nouveau/nv50/nv50_program.c
View file

@ -256,7 +256,7 @@ static int
nv50_program_assign_varying_slots(struct nv50_ir_prog_info_out *info)
{
switch (info->type) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
return nv50_vertprog_assign_slots(info);
case PIPE_SHADER_GEOMETRY:
return nv50_vertprog_assign_slots(info);
@ -332,7 +332,7 @@ nv50_program_translate(struct nv50_program *prog, uint16_t chipset,
struct nv50_ir_prog_info *info;
struct nv50_ir_prog_info_out info_out = {};
int i, ret;
const uint8_t map_undef = (prog->type == PIPE_SHADER_VERTEX) ? 0x40 : 0x80;
const uint8_t map_undef = (prog->type == MESA_SHADER_VERTEX) ? 0x40 : 0x80;
info = CALLOC_STRUCT(nv50_ir_prog_info);
if (!info)
@ -465,7 +465,7 @@ nv50_program_upload_code(struct nv50_context *nv50, struct nv50_program *prog)
uint8_t prog_type;
switch (prog->type) {
case PIPE_SHADER_VERTEX: heap = nv50->screen->vp_code_heap; break;
case MESA_SHADER_VERTEX: heap = nv50->screen->vp_code_heap; break;
case PIPE_SHADER_GEOMETRY: heap = nv50->screen->gp_code_heap; break;
case PIPE_SHADER_FRAGMENT: heap = nv50->screen->fp_code_heap; break;
case PIPE_SHADER_COMPUTE: heap = nv50->screen->fp_code_heap; break;

2
src/gallium/drivers/nouveau/nv50/nv50_screen.c
View file

@ -116,7 +116,7 @@ nv50_init_shader_caps(struct nv50_screen *screen)
caps->max_tex_instructions =
caps->max_tex_indirections = 16384;
caps->max_control_flow_depth = 4;
caps->max_inputs = i == PIPE_SHADER_VERTEX ? 32 : 15;
caps->max_inputs = i == MESA_SHADER_VERTEX ? 32 : 15;
caps->max_outputs = 16;
caps->max_const_buffer0_size = 65536;
caps->max_const_buffers = NV50_MAX_PIPE_CONSTBUFS;

2
src/gallium/drivers/nouveau/nv50/nv50_state.c
View file

@ -782,7 +782,7 @@ static void *
nv50_vp_state_create(struct pipe_context *pipe,
const struct pipe_shader_state *cso)
{
return nv50_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
return nv50_sp_state_create(pipe, cso, MESA_SHADER_VERTEX);
}
static void

2
src/gallium/drivers/nouveau/nv50/nv50_surface.c
View file

@ -815,7 +815,7 @@ nv50_blitter_make_vp(struct nv50_blitter *blit)
0x10000811, 0x0423c789, /* mov b32 o[0x10] s[0x10] */ /* TEXC.z */
};
blit->vp.type = PIPE_SHADER_VERTEX;
blit->vp.type = MESA_SHADER_VERTEX;
blit->vp.translated = true;
blit->vp.code = (uint32_t *)code; /* const_cast */
blit->vp.code_size = sizeof(code);

2
src/gallium/drivers/nouveau/nvc0/nvc0_context.h
View file

@ -296,7 +296,7 @@ static inline unsigned
nvc0_shader_stage(unsigned pipe)
{
switch (pipe) {
case PIPE_SHADER_VERTEX: return 0;
case MESA_SHADER_VERTEX: return 0;
case PIPE_SHADER_TESS_CTRL: return 1;
case PIPE_SHADER_TESS_EVAL: return 2;
case PIPE_SHADER_GEOMETRY: return 3;

4
src/gallium/drivers/nouveau/nvc0/nvc0_program.c
View file

@ -186,7 +186,7 @@ nvc0_program_assign_varying_slots(struct nv50_ir_prog_info_out *info)
{
int ret;
if (info->type == PIPE_SHADER_VERTEX)
if (info->type == MESA_SHADER_VERTEX)
ret = nvc0_vp_assign_input_slots(info);
else
ret = nvc0_sp_assign_input_slots(info);
@ -690,7 +690,7 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
prog->vp.edgeflag = info_out.io.edgeFlagIn;
switch (prog->type) {
case PIPE_SHADER_VERTEX:
case MESA_SHADER_VERTEX:
ret = nvc0_vp_gen_header(prog, &info_out);
break;
case PIPE_SHADER_TESS_CTRL:

2
src/gallium/drivers/nouveau/nvc0/nvc0_state.c
View file

@ -639,7 +639,7 @@ static void *
nvc0_vp_state_create(struct pipe_context *pipe,
const struct pipe_shader_state *cso)
{
return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
return nvc0_sp_state_create(pipe, cso, MESA_SHADER_VERTEX);
}
static void

2
src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
View file

@ -856,7 +856,7 @@ nvc0_blitter_make_vp(struct pipe_context *pipe)
{
const nir_shader_compiler_options *options =
nv50_ir_nir_shader_compiler_options(nouveau_screen(pipe->screen)->device->chipset,
PIPE_SHADER_VERTEX);
MESA_SHADER_VERTEX);
struct nir_builder b =
nir_builder_init_simple_shader(MESA_SHADER_VERTEX, options,

2
src/gallium/drivers/panfrost/pan_blit.c
View file

@ -43,7 +43,7 @@ panfrost_blitter_save(struct panfrost_context *ctx,
util_last_bit(ctx->vb_mask));
util_blitter_save_vertex_elements(blitter, ctx->vertex);
util_blitter_save_vertex_shader(blitter,
ctx->uncompiled[PIPE_SHADER_VERTEX]);
ctx->uncompiled[MESA_SHADER_VERTEX]);
util_blitter_save_rasterizer(blitter, ctx->rasterizer);
util_blitter_save_viewport(blitter, &ctx->pipe_viewport);
util_blitter_save_so_targets(blitter, 0, NULL, 0);

102
src/gallium/drivers/panfrost/pan_cmdstream.c
View file

@ -419,8 +419,8 @@ panfrost_emit_compute_shader_meta(struct panfrost_batch *batch,
{
struct panfrost_compiled_shader *ss = batch->ctx->prog[stage];
panfrost_batch_add_bo(batch, ss->bin.bo, PIPE_SHADER_VERTEX);
panfrost_batch_add_bo(batch, ss->state.bo, PIPE_SHADER_VERTEX);
panfrost_batch_add_bo(batch, ss->bin.bo, MESA_SHADER_VERTEX);
panfrost_batch_add_bo(batch, ss->state.bo, MESA_SHADER_VERTEX);
return ss->state.gpu;
}
@ -944,7 +944,7 @@ panfrost_emit_vertex_buffers(struct panfrost_batch *batch)
struct panfrost_resource *rsrc = pan_resource(prsrc);
assert(!vb.is_user_buffer);
panfrost_batch_read_rsrc(batch, rsrc, PIPE_SHADER_VERTEX);
panfrost_batch_read_rsrc(batch, rsrc, MESA_SHADER_VERTEX);
pan_pack(buffers + i, BUFFER, cfg) {
cfg.address = rsrc->plane.base + vb.buffer_offset;
@ -1308,7 +1308,7 @@ panfrost_upload_sysvals(struct panfrost_batch *batch, void *ptr_cpu,
case PAN_SYSVAL_XFB: {
unsigned buf = PAN_SYSVAL_ID(sysval);
struct panfrost_compiled_shader *vs =
batch->ctx->prog[PIPE_SHADER_VERTEX];
batch->ctx->prog[MESA_SHADER_VERTEX];
struct pipe_stream_output_info *so = &vs->stream_output;
unsigned stride = so->stride[buf] * 4;
@ -1328,7 +1328,7 @@ panfrost_upload_sysvals(struct panfrost_batch *batch, void *ptr_cpu,
util_range_add(&rsrc->base, &rsrc->valid_buffer_range, offset,
target->buffer_size - offset);
panfrost_batch_write_rsrc(batch, rsrc, PIPE_SHADER_VERTEX);
panfrost_batch_write_rsrc(batch, rsrc, MESA_SHADER_VERTEX);
uniforms[i].du[0] = rsrc->plane.base + offset;
break;
@ -2164,9 +2164,9 @@ panfrost_emit_vertex_data(struct panfrost_batch *batch, uint64_t *buffers)
{
struct panfrost_context *ctx = batch->ctx;
struct panfrost_vertex_state *so = ctx->vertex;
struct panfrost_compiled_shader *vs = ctx->prog[PIPE_SHADER_VERTEX];
struct panfrost_compiled_shader *vs = ctx->prog[MESA_SHADER_VERTEX];
bool instanced = ctx->instance_count > 1;
uint32_t image_mask = ctx->image_mask[PIPE_SHADER_VERTEX];
uint32_t image_mask = ctx->image_mask[MESA_SHADER_VERTEX];
unsigned nr_images = util_last_bit(image_mask);
/* Worst case: everything is NPOT, which is only possible if instancing
@ -2180,7 +2180,7 @@ panfrost_emit_vertex_data(struct panfrost_batch *batch, uint64_t *buffers)
unsigned count = vs->info.attribute_count;
struct panfrost_compiled_shader *xfb =
ctx->uncompiled[PIPE_SHADER_VERTEX]->xfb;
ctx->uncompiled[MESA_SHADER_VERTEX]->xfb;
if (xfb)
count = MAX2(count, xfb->info.attribute_count);
@ -2226,7 +2226,7 @@ panfrost_emit_vertex_data(struct panfrost_batch *batch, uint64_t *buffers)
if (!rsrc)
continue;
panfrost_batch_read_rsrc(batch, rsrc, PIPE_SHADER_VERTEX);
panfrost_batch_read_rsrc(batch, rsrc, MESA_SHADER_VERTEX);
/* Mask off lower bits, see offset fixup below */
uint64_t raw_addr = rsrc->plane.base + buf->buffer_offset;
@ -2326,9 +2326,9 @@ panfrost_emit_vertex_data(struct panfrost_batch *batch, uint64_t *buffers)
if (nr_images) {
k = ALIGN_POT(k, 2);
emit_image_attribs(ctx, PIPE_SHADER_VERTEX, out + so->num_elements, k);
emit_image_bufs(batch, PIPE_SHADER_VERTEX, bufs + k, k);
k += (util_last_bit(ctx->image_mask[PIPE_SHADER_VERTEX]) * 2);
emit_image_attribs(ctx, MESA_SHADER_VERTEX, out + so->num_elements, k);
emit_image_bufs(batch, MESA_SHADER_VERTEX, bufs + k, k);
k += (util_last_bit(ctx->image_mask[MESA_SHADER_VERTEX]) * 2);
}
#if PAN_ARCH >= 6
@ -2681,7 +2681,7 @@ panfrost_emit_varying_descriptor(struct panfrost_batch *batch,
bool point_coord_replace)
{
struct panfrost_context *ctx = batch->ctx;
struct panfrost_compiled_shader *vs = ctx->prog[PIPE_SHADER_VERTEX];
struct panfrost_compiled_shader *vs = ctx->prog[MESA_SHADER_VERTEX];
struct panfrost_compiled_shader *fs = ctx->prog[PIPE_SHADER_FRAGMENT];
uint16_t point_coord_mask = 0;
@ -2932,7 +2932,7 @@ static uint64_t
panfrost_emit_varying_descriptors(struct panfrost_batch *batch)
{
struct panfrost_compiled_shader *vs =
batch->ctx->prog[PIPE_SHADER_VERTEX];
batch->ctx->prog[MESA_SHADER_VERTEX];
struct panfrost_compiled_shader *fs =
batch->ctx->prog[PIPE_SHADER_FRAGMENT];
@ -3043,7 +3043,7 @@ panfrost_update_shader_state(struct panfrost_batch *batch,
/* Vertex shaders need to mix vertex data and image descriptors in the
* attribute array. This is taken care of in panfrost_update_state_3d().
*/
if (st != PIPE_SHADER_VERTEX && (dirty & PAN_DIRTY_STAGE_IMAGE)) {
if (st != MESA_SHADER_VERTEX && (dirty & PAN_DIRTY_STAGE_IMAGE)) {
batch->attribs[st] =
panfrost_emit_image_attribs(batch, &batch->attrib_bufs[st], st);
}
@ -3074,14 +3074,14 @@ panfrost_update_state_3d(struct panfrost_batch *batch)
batch->blend = panfrost_emit_blend_valhall(batch);
if (dirty & PAN_DIRTY_VERTEX) {
batch->attribs[PIPE_SHADER_VERTEX] = panfrost_emit_vertex_data(batch);
batch->attribs[MESA_SHADER_VERTEX] = panfrost_emit_vertex_data(batch);
batch->attrib_bufs[PIPE_SHADER_VERTEX] =
batch->attrib_bufs[MESA_SHADER_VERTEX] =
panfrost_emit_vertex_buffers(batch);
}
#else
unsigned vt_shader_dirty = ctx->dirty_shader[PIPE_SHADER_VERTEX];
struct panfrost_compiled_shader *vs = ctx->prog[PIPE_SHADER_VERTEX];
unsigned vt_shader_dirty = ctx->dirty_shader[MESA_SHADER_VERTEX];
struct panfrost_compiled_shader *vs = ctx->prog[MESA_SHADER_VERTEX];
struct panfrost_vertex_state *vstate = ctx->vertex;
bool attr_offsetted_by_instance_base =
vstate->attr_depends_on_base_instance_mask &
@ -3093,8 +3093,8 @@ panfrost_update_state_3d(struct panfrost_batch *batch)
if ((dirty & PAN_DIRTY_VERTEX) ||
(vt_shader_dirty & (PAN_DIRTY_STAGE_IMAGE | PAN_DIRTY_STAGE_SHADER)) ||
attr_offsetted_by_instance_base) {
batch->attribs[PIPE_SHADER_VERTEX] = panfrost_emit_vertex_data(
batch, &batch->attrib_bufs[PIPE_SHADER_VERTEX]);
batch->attribs[MESA_SHADER_VERTEX] = panfrost_emit_vertex_data(
batch, &batch->attrib_bufs[MESA_SHADER_VERTEX]);
}
#endif
}
@ -3118,40 +3118,40 @@ panfrost_launch_xfb(struct panfrost_batch *batch,
perf_debug(batch->ctx, "Emulating transform feedback");
struct panfrost_uncompiled_shader *vs_uncompiled =
ctx->uncompiled[PIPE_SHADER_VERTEX];
struct panfrost_compiled_shader *vs = ctx->prog[PIPE_SHADER_VERTEX];
ctx->uncompiled[MESA_SHADER_VERTEX];
struct panfrost_compiled_shader *vs = ctx->prog[MESA_SHADER_VERTEX];
vs_uncompiled->xfb->stream_output = vs->stream_output;
uint64_t saved_rsd = batch->rsd[PIPE_SHADER_VERTEX];
uint64_t saved_ubo = batch->uniform_buffers[PIPE_SHADER_VERTEX];
uint64_t saved_push = batch->push_uniforms[PIPE_SHADER_VERTEX];
uint64_t saved_rsd = batch->rsd[MESA_SHADER_VERTEX];
uint64_t saved_ubo = batch->uniform_buffers[MESA_SHADER_VERTEX];
uint64_t saved_push = batch->push_uniforms[MESA_SHADER_VERTEX];
unsigned saved_nr_push_uniforms =
batch->nr_push_uniforms[PIPE_SHADER_VERTEX];
batch->nr_push_uniforms[MESA_SHADER_VERTEX];
unsigned saved_nr_ubos =
batch->nr_uniform_buffers[PIPE_SHADER_VERTEX];
batch->nr_uniform_buffers[MESA_SHADER_VERTEX];
ctx->uncompiled[PIPE_SHADER_VERTEX] = NULL; /* should not be read */
ctx->prog[PIPE_SHADER_VERTEX] = vs_uncompiled->xfb;
batch->rsd[PIPE_SHADER_VERTEX] =
panfrost_emit_compute_shader_meta(batch, PIPE_SHADER_VERTEX);
ctx->uncompiled[MESA_SHADER_VERTEX] = NULL; /* should not be read */
ctx->prog[MESA_SHADER_VERTEX] = vs_uncompiled->xfb;
batch->rsd[MESA_SHADER_VERTEX] =
panfrost_emit_compute_shader_meta(batch, MESA_SHADER_VERTEX);
batch->uniform_buffers[PIPE_SHADER_VERTEX] =
panfrost_emit_const_buf(batch, PIPE_SHADER_VERTEX,
&batch->nr_uniform_buffers[PIPE_SHADER_VERTEX],
&batch->push_uniforms[PIPE_SHADER_VERTEX],
&batch->nr_push_uniforms[PIPE_SHADER_VERTEX]);
batch->uniform_buffers[MESA_SHADER_VERTEX] =
panfrost_emit_const_buf(batch, MESA_SHADER_VERTEX,
&batch->nr_uniform_buffers[MESA_SHADER_VERTEX],
&batch->push_uniforms[MESA_SHADER_VERTEX],
&batch->nr_push_uniforms[MESA_SHADER_VERTEX]);
JOBX(launch_xfb)(batch, info, count);
batch->compute_count++;
ctx->uncompiled[PIPE_SHADER_VERTEX] = vs_uncompiled;
ctx->prog[PIPE_SHADER_VERTEX] = vs;
batch->rsd[PIPE_SHADER_VERTEX] = saved_rsd;
batch->uniform_buffers[PIPE_SHADER_VERTEX] = saved_ubo;
batch->push_uniforms[PIPE_SHADER_VERTEX] = saved_push;
batch->nr_push_uniforms[PIPE_SHADER_VERTEX] = saved_nr_push_uniforms;
batch->nr_uniform_buffers[PIPE_SHADER_VERTEX] = saved_nr_ubos;
ctx->uncompiled[MESA_SHADER_VERTEX] = vs_uncompiled;
ctx->prog[MESA_SHADER_VERTEX] = vs;
batch->rsd[MESA_SHADER_VERTEX] = saved_rsd;
batch->uniform_buffers[MESA_SHADER_VERTEX] = saved_ubo;
batch->push_uniforms[MESA_SHADER_VERTEX] = saved_push;
batch->nr_push_uniforms[MESA_SHADER_VERTEX] = saved_nr_push_uniforms;
batch->nr_uniform_buffers[MESA_SHADER_VERTEX] = saved_nr_ubos;
}
/*
@ -3263,7 +3263,7 @@ panfrost_single_draw_direct(struct panfrost_batch *batch,
ctx->base_instance = info->start_instance;
ctx->drawid = drawid_offset;
struct panfrost_compiled_shader *vs = ctx->prog[PIPE_SHADER_VERTEX];
struct panfrost_compiled_shader *vs = ctx->prog[MESA_SHADER_VERTEX];
bool idvs = vs->info.vs.idvs;
UNUSED unsigned vertex_count =
@ -3272,11 +3272,11 @@ panfrost_single_draw_direct(struct panfrost_batch *batch,
panfrost_statistics_record(ctx, info, draw);
panfrost_update_state_3d(batch);
panfrost_update_shader_state(batch, PIPE_SHADER_VERTEX);
panfrost_update_shader_state(batch, MESA_SHADER_VERTEX);
panfrost_update_shader_state(batch, PIPE_SHADER_FRAGMENT);
panfrost_clean_state_3d(ctx);
if (ctx->uncompiled[PIPE_SHADER_VERTEX]->xfb) {
if (ctx->uncompiled[MESA_SHADER_VERTEX]->xfb) {
panfrost_launch_xfb(batch, info, draw->count);
}
@ -3402,7 +3402,7 @@ panfrost_draw_indirect(struct pipe_context *pipe,
struct pipe_draw_info tmp_info = *info;
panfrost_batch_read_rsrc(batch, pan_resource(indirect->buffer),
PIPE_SHADER_VERTEX);
MESA_SHADER_VERTEX);
panfrost_update_active_prim(ctx, &tmp_info);
@ -3412,12 +3412,12 @@ panfrost_draw_indirect(struct pipe_context *pipe,
if (info->index_size) {
struct panfrost_resource *index_buffer =
pan_resource(info->index.resource);
panfrost_batch_read_rsrc(batch, index_buffer, PIPE_SHADER_VERTEX);
panfrost_batch_read_rsrc(batch, index_buffer, MESA_SHADER_VERTEX);
batch->indices = index_buffer->plane.base;
}
panfrost_update_state_3d(batch);
panfrost_update_shader_state(batch, PIPE_SHADER_VERTEX);
panfrost_update_shader_state(batch, MESA_SHADER_VERTEX);
panfrost_update_shader_state(batch, PIPE_SHADER_FRAGMENT);
panfrost_clean_state_3d(ctx);
@ -4367,7 +4367,7 @@ batch_get_polygon_list(struct panfrost_batch *batch)
bool init_polygon_list = !has_draws;
batch->polygon_list_bo = panfrost_batch_create_bo(
batch, size, init_polygon_list ? 0 : PAN_BO_INVISIBLE,
PIPE_SHADER_VERTEX, "Polygon list");
MESA_SHADER_VERTEX, "Polygon list");
if (!batch->polygon_list_bo) {
mesa_loge("failed to allocate memory for polygon-list");

6
src/gallium/drivers/panfrost/pan_cmdstream.h
View file

@ -249,7 +249,7 @@ panfrost_get_position_shader(struct panfrost_batch *batch,
const struct pipe_draw_info *info)
{
/* IDVS/points vertex shader */
uint64_t vs_ptr = batch->rsd[PIPE_SHADER_VERTEX];
uint64_t vs_ptr = batch->rsd[MESA_SHADER_VERTEX];
/* IDVS/triangle vertex shader */
if (vs_ptr && info->mode != MESA_PRIM_POINTS)
@ -262,7 +262,7 @@ panfrost_get_position_shader(struct panfrost_batch *batch,
static inline uint64_t
panfrost_get_varying_shader(struct panfrost_batch *batch)
{
return batch->rsd[PIPE_SHADER_VERTEX] + (2 * pan_size(SHADER_PROGRAM));
return batch->rsd[MESA_SHADER_VERTEX] + (2 * pan_size(SHADER_PROGRAM));
}
#endif
@ -314,7 +314,7 @@ panfrost_emit_resources(struct panfrost_batch *batch,
if (stage == PIPE_SHADER_FRAGMENT) {
pan_make_resource_table(T, PAN_TABLE_ATTRIBUTE, batch->attribs[stage],
batch->nr_varying_attribs[PIPE_SHADER_FRAGMENT]);
} else if (stage == PIPE_SHADER_VERTEX) {
} else if (stage == MESA_SHADER_VERTEX) {
pan_make_resource_table(T, PAN_TABLE_ATTRIBUTE, batch->attribs[stage],
ctx->vertex->num_elements);

2
src/gallium/drivers/panfrost/pan_context.c
View file

@ -97,7 +97,7 @@ panfrost_clear(struct pipe_context *pipe, unsigned buffers,
bool
panfrost_writes_point_size(struct panfrost_context *ctx)
{
struct panfrost_compiled_shader *vs = ctx->prog[PIPE_SHADER_VERTEX];
struct panfrost_compiled_shader *vs = ctx->prog[MESA_SHADER_VERTEX];
assert(vs != NULL);
return vs->info.vs.writes_point_size && ctx->active_prim == MESA_PRIM_POINTS;

14
src/gallium/drivers/panfrost/pan_csf.c
View file

@ -905,7 +905,7 @@ csf_emit_shader_regs(struct panfrost_batch *batch, enum pipe_shader_type stage,
{
uint64_t resources = panfrost_emit_resources(batch, stage);
assert(stage == PIPE_SHADER_VERTEX || stage == PIPE_SHADER_FRAGMENT ||
assert(stage == MESA_SHADER_VERTEX || stage == PIPE_SHADER_FRAGMENT ||
stage == PIPE_SHADER_COMPUTE);
#if PAN_ARCH >= 12
@ -1079,8 +1079,8 @@ GENX(csf_launch_xfb)(struct panfrost_batch *batch,
cs_move32_to(b, cs_sr_reg32(b, COMPUTE, JOB_SIZE_Y), info->instance_count);
cs_move32_to(b, cs_sr_reg32(b, COMPUTE, JOB_SIZE_Z), 1);
csf_emit_shader_regs(batch, PIPE_SHADER_VERTEX,
batch->rsd[PIPE_SHADER_VERTEX]);
csf_emit_shader_regs(batch, MESA_SHADER_VERTEX,
batch->rsd[MESA_SHADER_VERTEX]);
/* force a barrier to avoid read/write sync issues with buffers */
cs_wait_slot(b, 2);
@ -1114,7 +1114,7 @@ csf_emit_draw_state(struct panfrost_batch *batch,
const struct pipe_draw_info *info, unsigned drawid_offset)
{
struct panfrost_context *ctx = batch->ctx;
struct panfrost_compiled_shader *vs = ctx->prog[PIPE_SHADER_VERTEX];
struct panfrost_compiled_shader *vs = ctx->prog[MESA_SHADER_VERTEX];
struct panfrost_compiled_shader *fs = ctx->prog[PIPE_SHADER_FRAGMENT];
bool idvs = vs->info.vs.idvs;
@ -1131,7 +1131,7 @@ csf_emit_draw_state(struct panfrost_batch *batch,
cs_vt_start(batch->csf.cs.builder, cs_now());
}
csf_emit_shader_regs(batch, PIPE_SHADER_VERTEX,
csf_emit_shader_regs(batch, MESA_SHADER_VERTEX,
panfrost_get_position_shader(batch, info));
if (fs_required) {
@ -1357,7 +1357,7 @@ csf_emit_draw_id_register(struct panfrost_batch *batch, unsigned offset)
{
struct cs_builder *b = batch->csf.cs.builder;
struct panfrost_context *ctx = batch->ctx;
struct panfrost_uncompiled_shader *vs = ctx->uncompiled[PIPE_SHADER_VERTEX];
struct panfrost_uncompiled_shader *vs = ctx->uncompiled[MESA_SHADER_VERTEX];
if (!BITSET_TEST(vs->nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID))
return cs_undef();
@ -1695,5 +1695,5 @@ GENX(csf_emit_write_timestamp)(struct panfrost_batch *batch,
cs_move64_to(b, address, dst->plane.base + offset);
cs_store_state(b, address, 0, MALI_CS_STATE_TIMESTAMP, cs_now());
panfrost_batch_write_rsrc(batch, dst, PIPE_SHADER_VERTEX);
panfrost_batch_write_rsrc(batch, dst, MESA_SHADER_VERTEX);
}

2
src/gallium/drivers/panfrost/pan_helpers.c
View file

@ -104,7 +104,7 @@ panfrost_get_index_buffer(struct panfrost_batch *batch,
if (!info->has_user_indices) {
/* Only resources can be directly mapped */
panfrost_batch_read_rsrc(batch, rsrc, PIPE_SHADER_VERTEX);
panfrost_batch_read_rsrc(batch, rsrc, MESA_SHADER_VERTEX);
return rsrc->plane.base + offset;
} else {
/* Otherwise, we need to upload to transient memory */

22
src/gallium/drivers/panfrost/pan_jm.c
View file

@ -468,13 +468,13 @@ jm_emit_vertex_draw(struct panfrost_batch *batch,
struct mali_draw_packed *section)
{
pan_pack(section, DRAW, cfg) {
cfg.state = batch->rsd[PIPE_SHADER_VERTEX];
cfg.attributes = batch->attribs[PIPE_SHADER_VERTEX];
cfg.attribute_buffers = batch->attrib_bufs[PIPE_SHADER_VERTEX];
cfg.state = batch->rsd[MESA_SHADER_VERTEX];
cfg.attributes = batch->attribs[MESA_SHADER_VERTEX];
cfg.attribute_buffers = batch->attrib_bufs[MESA_SHADER_VERTEX];
cfg.varyings = batch->varyings.vs;
cfg.varying_buffers = cfg.varyings ? batch->varyings.bufs : 0;
cfg.thread_storage = batch->tls.gpu;
jm_emit_draw_descs(batch, &cfg, PIPE_SHADER_VERTEX);
jm_emit_draw_descs(batch, &cfg, MESA_SHADER_VERTEX);
}
}
@ -758,7 +758,7 @@ jm_emit_malloc_vertex_job(struct panfrost_batch *batch,
bool secondary_shader, void *job)
{
struct panfrost_context *ctx = batch->ctx;
struct panfrost_compiled_shader *vs = ctx->prog[PIPE_SHADER_VERTEX];
struct panfrost_compiled_shader *vs = ctx->prog[MESA_SHADER_VERTEX];
struct panfrost_compiled_shader *fs = ctx->prog[PIPE_SHADER_FRAGMENT];
bool fs_required = panfrost_fs_required(
@ -808,7 +808,7 @@ jm_emit_malloc_vertex_job(struct panfrost_batch *batch,
fs_required, u_reduced_prim(info->mode));
pan_section_pack(job, MALLOC_VERTEX_JOB, POSITION, cfg) {
jm_emit_shader_env(batch, &cfg, PIPE_SHADER_VERTEX,
jm_emit_shader_env(batch, &cfg, MESA_SHADER_VERTEX,
panfrost_get_position_shader(batch, info));
}
@ -820,7 +820,7 @@ jm_emit_malloc_vertex_job(struct panfrost_batch *batch,
if (!secondary_shader)
continue;
jm_emit_shader_env(batch, &cfg, PIPE_SHADER_VERTEX,
jm_emit_shader_env(batch, &cfg, MESA_SHADER_VERTEX,
panfrost_get_varying_shader(batch));
}
}
@ -876,8 +876,8 @@ GENX(jm_launch_xfb)(struct panfrost_batch *batch,
cfg.workgroup_count_y = info->instance_count;
cfg.workgroup_count_z = 1;
jm_emit_shader_env(batch, &cfg.compute, PIPE_SHADER_VERTEX,
batch->rsd[PIPE_SHADER_VERTEX]);
jm_emit_shader_env(batch, &cfg.compute, MESA_SHADER_VERTEX,
batch->rsd[MESA_SHADER_VERTEX]);
/* TODO: Indexing. Also, this is a legacy feature... */
cfg.compute.attribute_offset = batch->ctx->offset_start;
@ -938,7 +938,7 @@ GENX(jm_launch_draw)(struct panfrost_batch *batch,
unsigned vertex_count)
{
struct panfrost_context *ctx = batch->ctx;
struct panfrost_compiled_shader *vs = ctx->prog[PIPE_SHADER_VERTEX];
struct panfrost_compiled_shader *vs = ctx->prog[MESA_SHADER_VERTEX];
bool secondary_shader = vs->info.vs.secondary_enable;
bool idvs = vs->info.vs.idvs;
@ -1030,5 +1030,5 @@ GENX(jm_emit_write_timestamp)(struct panfrost_batch *batch,
pan_jc_add_job(&batch->jm.jobs.vtc_jc, MALI_JOB_TYPE_WRITE_VALUE, false,
false, 0, 0, &job, false);
panfrost_batch_write_rsrc(batch, dst, PIPE_SHADER_VERTEX);
panfrost_batch_write_rsrc(batch, dst, MESA_SHADER_VERTEX);
}

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