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rusticl: enable proper fp16 support
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Adam Jackson <ajax@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34053>
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6 changed files with 5 additions and 10 deletions
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@ -1186,7 +1186,6 @@ Rusticl environment variables
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a comma-separated list of features to enable. Those are disabled by default
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a comma-separated list of features to enable. Those are disabled by default
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as they might not be stable enough or break OpenCL conformance.
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as they might not be stable enough or break OpenCL conformance.
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- ``fp16`` enables OpenCL half support
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- ``fp64`` enables OpenCL double support
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- ``fp64`` enables OpenCL double support
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- ``intel`` enables various Intel OpenCL extensions
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- ``intel`` enables various Intel OpenCL extensions
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@ -819,7 +819,7 @@ Rusticl extensions that are not part of any OpenCL version:
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cl_khr_expect_assume in progress (hints are ignored)
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cl_khr_expect_assume in progress (hints are ignored)
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cl_khr_extended_async_copies not started
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cl_khr_extended_async_copies not started
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cl_khr_extended_bit_ops in progress
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cl_khr_extended_bit_ops in progress
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cl_khr_fp16 in progress (llvmpipe, radeonsi, zink, Available with environment variable RUSTICL_FEATURES=fp16)
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cl_khr_fp16 DONE (asahi, freedreno, llvmpipe, panfrost, radeonsi, zink)
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cl_khr_gl_depth_images not started
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cl_khr_gl_depth_images not started
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cl_khr_gl_msaa_sharing not started
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cl_khr_gl_msaa_sharing not started
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cl_khr_gl_sharing DONE (iris, radeonsi, zink)
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cl_khr_gl_sharing DONE (iris, radeonsi, zink)
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@ -36,3 +36,4 @@ VK_KHR_load_store_op_none on panvk
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VK_EXT_load_store_op_none on panvk
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VK_EXT_load_store_op_none on panvk
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VK_EXT_scalar_block_layout on radv/gfx6
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VK_EXT_scalar_block_layout on radv/gfx6
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VK_EXT_inline_uniform_block on panvk
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VK_EXT_inline_uniform_block on panvk
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cl_khr_fp16 on asahi, freedreno, llvmpipe, panfrost, radeonsi and zink
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@ -888,10 +888,6 @@ impl Device {
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}
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}
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pub fn fp16_supported(&self) -> bool {
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pub fn fp16_supported(&self) -> bool {
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if !Platform::features().fp16 {
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return false;
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}
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self.shader_caps().fp16
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self.shader_caps().fp16
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}
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}
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@ -67,7 +67,6 @@ pub struct PlatformDebug {
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}
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}
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pub struct PlatformFeatures {
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pub struct PlatformFeatures {
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pub fp16: bool,
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pub fp64: bool,
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pub fp64: bool,
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pub intel: bool,
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pub intel: bool,
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}
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}
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@ -96,7 +95,6 @@ static mut PLATFORM_DBG: PlatformDebug = PlatformDebug {
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validate_spirv: false,
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validate_spirv: false,
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};
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};
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static mut PLATFORM_FEATURES: PlatformFeatures = PlatformFeatures {
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static mut PLATFORM_FEATURES: PlatformFeatures = PlatformFeatures {
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fp16: false,
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fp64: false,
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fp64: false,
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intel: false,
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intel: false,
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};
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};
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@ -134,7 +132,6 @@ fn load_env() {
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if let Ok(feature_flags) = env::var("RUSTICL_FEATURES") {
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if let Ok(feature_flags) = env::var("RUSTICL_FEATURES") {
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for flag in feature_flags.split(',') {
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for flag in feature_flags.split(',') {
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match flag {
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match flag {
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"fp16" => features.fp16 = true,
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"fp64" => features.fp64 = true,
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"fp64" => features.fp64 = true,
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"intel" => features.intel = true,
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"intel" => features.intel = true,
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"" => (),
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"" => (),
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@ -518,7 +518,9 @@ impl CLCSpecConstantType for clc_spec_constant_type {
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Self::CLC_SPEC_CONSTANT_INT32
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Self::CLC_SPEC_CONSTANT_INT32
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| Self::CLC_SPEC_CONSTANT_UINT32
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| Self::CLC_SPEC_CONSTANT_UINT32
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| Self::CLC_SPEC_CONSTANT_FLOAT => 4,
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| Self::CLC_SPEC_CONSTANT_FLOAT => 4,
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Self::CLC_SPEC_CONSTANT_INT16 | Self::CLC_SPEC_CONSTANT_UINT16 => 2,
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Self::CLC_SPEC_CONSTANT_INT16
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| Self::CLC_SPEC_CONSTANT_UINT16
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| Self::CLC_SPEC_CONSTANT_HALF => 2,
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Self::CLC_SPEC_CONSTANT_INT8
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Self::CLC_SPEC_CONSTANT_INT8
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| Self::CLC_SPEC_CONSTANT_UINT8
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| Self::CLC_SPEC_CONSTANT_UINT8
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| Self::CLC_SPEC_CONSTANT_BOOL => 1,
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| Self::CLC_SPEC_CONSTANT_BOOL => 1,
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