From cf3ec8d3b907321692c80db20a40c6d38c748f62 Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Thu, 13 Mar 2025 17:49:15 +0100 Subject: [PATCH] rusticl: enable proper fp16 support Reviewed-by: Alyssa Rosenzweig Reviewed-by: Adam Jackson Part-of: --- docs/envvars.rst | 1 - docs/features.txt | 2 +- docs/relnotes/new_features.txt | 1 + src/gallium/frontends/rusticl/core/device.rs | 4 ---- src/gallium/frontends/rusticl/core/platform.rs | 3 --- src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs | 4 +++- 6 files changed, 5 insertions(+), 10 deletions(-) diff --git a/docs/envvars.rst b/docs/envvars.rst index ab8b0ba9416..1c3fbfc6b19 100644 --- a/docs/envvars.rst +++ b/docs/envvars.rst @@ -1186,7 +1186,6 @@ Rusticl environment variables a comma-separated list of features to enable. Those are disabled by default as they might not be stable enough or break OpenCL conformance. - - ``fp16`` enables OpenCL half support - ``fp64`` enables OpenCL double support - ``intel`` enables various Intel OpenCL extensions diff --git a/docs/features.txt b/docs/features.txt index 2de3d4ae5d4..c1fe9bb6c99 100644 --- a/docs/features.txt +++ b/docs/features.txt @@ -819,7 +819,7 @@ Rusticl extensions that are not part of any OpenCL version: cl_khr_expect_assume in progress (hints are ignored) cl_khr_extended_async_copies not started cl_khr_extended_bit_ops in progress - cl_khr_fp16 in progress (llvmpipe, radeonsi, zink, Available with environment variable RUSTICL_FEATURES=fp16) + cl_khr_fp16 DONE (asahi, freedreno, llvmpipe, panfrost, radeonsi, zink) cl_khr_gl_depth_images not started cl_khr_gl_msaa_sharing not started cl_khr_gl_sharing DONE (iris, radeonsi, zink) diff --git a/docs/relnotes/new_features.txt b/docs/relnotes/new_features.txt index 04c97d2db17..1ffb99392b0 100644 --- a/docs/relnotes/new_features.txt +++ b/docs/relnotes/new_features.txt @@ -36,3 +36,4 @@ VK_KHR_load_store_op_none on panvk VK_EXT_load_store_op_none on panvk VK_EXT_scalar_block_layout on radv/gfx6 VK_EXT_inline_uniform_block on panvk +cl_khr_fp16 on asahi, freedreno, llvmpipe, panfrost, radeonsi and zink diff --git a/src/gallium/frontends/rusticl/core/device.rs b/src/gallium/frontends/rusticl/core/device.rs index ade3f8fcbc2..d7e67522e23 100644 --- a/src/gallium/frontends/rusticl/core/device.rs +++ b/src/gallium/frontends/rusticl/core/device.rs @@ -888,10 +888,6 @@ impl Device { } pub fn fp16_supported(&self) -> bool { - if !Platform::features().fp16 { - return false; - } - self.shader_caps().fp16 } diff --git a/src/gallium/frontends/rusticl/core/platform.rs b/src/gallium/frontends/rusticl/core/platform.rs index bb0d4d98f62..f30591c7cd8 100644 --- a/src/gallium/frontends/rusticl/core/platform.rs +++ b/src/gallium/frontends/rusticl/core/platform.rs @@ -67,7 +67,6 @@ pub struct PlatformDebug { } pub struct PlatformFeatures { - pub fp16: bool, pub fp64: bool, pub intel: bool, } @@ -96,7 +95,6 @@ static mut PLATFORM_DBG: PlatformDebug = PlatformDebug { validate_spirv: false, }; static mut PLATFORM_FEATURES: PlatformFeatures = PlatformFeatures { - fp16: false, fp64: false, intel: false, }; @@ -134,7 +132,6 @@ fn load_env() { if let Ok(feature_flags) = env::var("RUSTICL_FEATURES") { for flag in feature_flags.split(',') { match flag { - "fp16" => features.fp16 = true, "fp64" => features.fp64 = true, "intel" => features.intel = true, "" => (), diff --git a/src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs b/src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs index 9c70cac28cb..cb021d6facf 100644 --- a/src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs +++ b/src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs @@ -518,7 +518,9 @@ impl CLCSpecConstantType for clc_spec_constant_type { Self::CLC_SPEC_CONSTANT_INT32 | Self::CLC_SPEC_CONSTANT_UINT32 | Self::CLC_SPEC_CONSTANT_FLOAT => 4, - Self::CLC_SPEC_CONSTANT_INT16 | Self::CLC_SPEC_CONSTANT_UINT16 => 2, + Self::CLC_SPEC_CONSTANT_INT16 + | Self::CLC_SPEC_CONSTANT_UINT16 + | Self::CLC_SPEC_CONSTANT_HALF => 2, Self::CLC_SPEC_CONSTANT_INT8 | Self::CLC_SPEC_CONSTANT_UINT8 | Self::CLC_SPEC_CONSTANT_BOOL => 1,