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radeonsi: lower nir_intrinsic_sparse_residency_code_and

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This is required by lower_tg4_offsets which split one
sparseTextureGatherOffsetsARB call to four sparseTextureGatherOffsetARB
calls and merge their resisident results into one.

Fixes: ee040a6b63 ("radeonsi: enable ARB_sparse_texture2")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16599>
This commit is contained in:
Qiang Yu 2022-05-18 11:17:20 +08:00 • committed by Marge Bot
parent 2fbbb8ad63
commit cc4d5b1666
1 changed files with 2 additions and 0 deletions
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2
src/gallium/drivers/radeonsi/si_shader_nir.c
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@ -205,6 +205,8 @@ lower_intrinsic_instr(nir_builder *b, nir_instr *instr, void *dummy)
case nir_intrinsic_is_sparse_texels_resident:
/* code==0 means sparse texels are resident */
return nir_ieq_imm(b, intrin->src[0].ssa, 0);
case nir_intrinsic_sparse_residency_code_and:
return nir_ior(b, intrin->src[0].ssa, intrin->src[1].ssa);
default:
return NULL;
}