From cc4d5b16661a156e6b3aa4170f7d8f7919efc270 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Wed, 18 May 2022 11:17:20 +0800 Subject: [PATCH] radeonsi: lower nir_intrinsic_sparse_residency_code_and MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is required by lower_tg4_offsets which split one sparseTextureGatherOffsetsARB call to four sparseTextureGatherOffsetARB calls and merge their resisident results into one. Fixes: ee040a6b639 ("radeonsi: enable ARB_sparse_texture2") Reviewed-by: Marek Olšák Signed-off-by: Qiang Yu Part-of: --- src/gallium/drivers/radeonsi/si_shader_nir.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c index d3bbc864b6e..612e75b8130 100644 --- a/src/gallium/drivers/radeonsi/si_shader_nir.c +++ b/src/gallium/drivers/radeonsi/si_shader_nir.c @@ -205,6 +205,8 @@ lower_intrinsic_instr(nir_builder *b, nir_instr *instr, void *dummy) case nir_intrinsic_is_sparse_texels_resident: /* code==0 means sparse texels are resident */ return nir_ieq_imm(b, intrin->src[0].ssa, 0); + case nir_intrinsic_sparse_residency_code_and: + return nir_ior(b, intrin->src[0].ssa, intrin->src[1].ssa); default: return NULL; }