From cc3cb526c4206811bf2f7e26001a7653d0b47388 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 8 Jul 2024 17:50:01 +0200 Subject: [PATCH] ac,radeonsi: add ac_is_reduction_mode_supported() Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/common/ac_formats.c | 34 +++++++++++++++++++++++++ src/amd/common/ac_formats.h | 4 +++ src/gallium/drivers/radeonsi/si_state.c | 29 +-------------------- 3 files changed, 39 insertions(+), 28 deletions(-) diff --git a/src/amd/common/ac_formats.c b/src/amd/common/ac_formats.c index a1f35894692..c24ea893001 100644 --- a/src/amd/common/ac_formats.c +++ b/src/amd/common/ac_formats.c @@ -766,3 +766,37 @@ ac_alpha_is_on_msb(const struct radeon_info *info, enum pipe_format format) return comp_swap != V_028C70_SWAP_STD_REV && comp_swap != V_028C70_SWAP_ALT_REV; } + +/* GFX6-8: + * - no integer format support + * - no depth format support (depth formats without shadow samplers are supported, + * but that's not enough) + * - only single-channel formats are supported + * - limitations of early chips (GFX6 only): no R9G9B9E5 support + * + * GFX9+: + * - all formats are supported + */ +bool +ac_is_reduction_mode_supported(const struct radeon_info *info, enum pipe_format format, + bool shadow_samplers) +{ + const struct util_format_description *desc = util_format_description(format); + + if (info->gfx_level <= GFX8) { + /* old HW limitations */ + if (info->gfx_level == GFX6 && format == PIPE_FORMAT_R9G9B9E5_FLOAT) + return false; + + /* reject if more than one channel */ + if (desc->nr_channels > 1) + return false; + + /* no integer or depth format support */ + if (util_format_is_pure_integer(format) || + (shadow_samplers && util_format_has_depth(desc))) + return false; + } + + return true; +} diff --git a/src/amd/common/ac_formats.h b/src/amd/common/ac_formats.h index 3b88bdb6ef1..80ef79b441f 100644 --- a/src/amd/common/ac_formats.h +++ b/src/amd/common/ac_formats.h @@ -66,6 +66,10 @@ ac_simplify_cb_format(enum pipe_format format); bool ac_alpha_is_on_msb(const struct radeon_info *info, enum pipe_format format); +bool +ac_is_reduction_mode_supported(const struct radeon_info *info, enum pipe_format format, + bool shadow_samplers); + #ifdef __cplusplus } #endif diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 2e935442d18..4d702b6466b 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2245,38 +2245,11 @@ static bool si_is_zs_format_supported(enum pipe_format format) return ac_is_zs_format_supported(format); } -/* GFX6-8: - * - no integer format support - * - no depth format support (depth formats without shadow samplers are supported, - * but that's not enough) - * - only single-channel formats are supported - * - limitations of early chips (GFX6 only): no R9G9B9E5 support - * - * GFX9+: - * - all formats are supported - */ static bool si_is_reduction_mode_supported(struct pipe_screen *screen, enum pipe_format format) { struct si_screen *sscreen = (struct si_screen *)screen; - const struct util_format_description *desc = util_format_description(format); - if (sscreen->info.gfx_level <= GFX8) { - /* old HW limitations */ - if (sscreen->info.gfx_level == GFX6 && - format == PIPE_FORMAT_R9G9B9E5_FLOAT) - return false; - - /* reject if more than one channel */ - if (desc->nr_channels > 1) - return false; - - /* no integer or depth format support */ - if (util_format_is_pure_integer(format) || - util_format_has_depth(desc)) - return false; - } - - return true; + return ac_is_reduction_mode_supported(&sscreen->info, format, true); } static bool si_is_format_supported(struct pipe_screen *screen, enum pipe_format format,