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ac/surface: fix address calculation for large images by using uint64_t

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also rename gfx9_surf_level -> gfx9_surf_meta_level

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23037>
This commit is contained in:
Marek Olšák 2023-05-15 11:59:43 -04:00 • committed by Marge Bot
parent ce161ce463
commit cbc6bf8218
2 changed files with 9 additions and 9 deletions
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2
src/amd/common/ac_surface.c
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@ -1777,7 +1777,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
*/
surf->u.gfx9.surf_slice_size =
MAX2(surf->u.gfx9.surf_slice_size,
surf->u.gfx9.surf_pitch * out.height * surf->bpe * surf->blk_w);
(uint64_t)surf->u.gfx9.surf_pitch * out.height * surf->bpe * surf->blk_w);
surf->surf_size = surf->u.gfx9.surf_slice_size * in->numSlices;
int alignment = 256 / surf->bpe;

16
src/amd/common/ac_surface.h
View file

@ -170,7 +170,7 @@ struct gfx9_surf_meta_flags {
uint8_t display_equation_valid : 1;
};
struct gfx9_surf_level {
struct gfx9_surf_meta_level {
unsigned offset;
unsigned size; /* the size of one level in one layer (the image is an array of layers
* where each layer has an array of levels) */
@ -245,7 +245,7 @@ struct gfx9_surf_layout {
/* The size of the 2D plane containing all mipmap levels. */
uint64_t surf_slice_size;
/* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
uint32_t offset[RADEON_SURF_MAX_LEVELS];
uint64_t offset[RADEON_SURF_MAX_LEVELS]; /* up to 16K * 16K * 16 * ~1.33 */
/* Mipmap level pitch in elements. Only valid for LINEAR. */
uint16_t pitch[RADEON_SURF_MAX_LEVELS];
@ -255,10 +255,10 @@ struct gfx9_surf_layout {
/* Pitch of level in blocks, only valid for prt images. */
uint16_t prt_level_pitch[RADEON_SURF_MAX_LEVELS];
/* Offset within slice in bytes, only valid for prt images. */
uint32_t prt_level_offset[RADEON_SURF_MAX_LEVELS];
uint64_t prt_level_offset[RADEON_SURF_MAX_LEVELS]; /* up to 64K * 64K * 16 * ~1.33 */
/* DCC or HTILE level info */
struct gfx9_surf_level meta_levels[RADEON_SURF_MAX_LEVELS];
struct gfx9_surf_meta_level meta_levels[RADEON_SURF_MAX_LEVELS];
union {
/* Color */
@ -288,7 +288,7 @@ struct gfx9_surf_layout {
void *dcc_retile_map;
/* CMASK level info (only level 0) */
struct gfx9_surf_level cmask_level0;
struct gfx9_surf_meta_level cmask_level0;
/* For DCC retiling. */
struct gfx9_meta_equation dcc_equation; /* 2D only */
@ -334,9 +334,9 @@ struct radeon_surf {
*/
/* Not supported yet for depth + stencil. */
uint16_t prt_tile_width;
uint16_t prt_tile_height;
uint16_t prt_tile_depth;
uint16_t prt_tile_width; /* up to 256 roughly (for 64KB tiles) */
uint16_t prt_tile_height; /* up to 256 roughly (for 64KB tiles) */
uint16_t prt_tile_depth; /* up to 32 roughly (for 64KB thick tiles) */
/* Tile swizzle can be OR'd with low bits of the BASE_256B address.
* The value is the same for all mipmap levels. Supported tile modes: