diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index bcca610201b..a14c1b681a4 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1777,7 +1777,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
        */
       surf->u.gfx9.surf_slice_size =
          MAX2(surf->u.gfx9.surf_slice_size,
-              surf->u.gfx9.surf_pitch * out.height * surf->bpe * surf->blk_w);
+              (uint64_t)surf->u.gfx9.surf_pitch * out.height * surf->bpe * surf->blk_w);
       surf->surf_size = surf->u.gfx9.surf_slice_size * in->numSlices;
 
       int alignment = 256 / surf->bpe;
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index f96283a9c56..070773b7999 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -170,7 +170,7 @@ struct gfx9_surf_meta_flags {
    uint8_t display_equation_valid : 1;
 };
 
-struct gfx9_surf_level {
+struct gfx9_surf_meta_level {
    unsigned offset;
    unsigned size; /* the size of one level in one layer (the image is an array of layers
                    * where each layer has an array of levels) */
@@ -245,7 +245,7 @@ struct gfx9_surf_layout {
    /* The size of the 2D plane containing all mipmap levels. */
    uint64_t surf_slice_size;
    /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
-   uint32_t offset[RADEON_SURF_MAX_LEVELS];
+   uint64_t offset[RADEON_SURF_MAX_LEVELS];  /* up to 16K * 16K * 16 * ~1.33 */
    /* Mipmap level pitch in elements. Only valid for LINEAR. */
    uint16_t pitch[RADEON_SURF_MAX_LEVELS];
 
@@ -255,10 +255,10 @@ struct gfx9_surf_layout {
    /* Pitch of level in blocks, only valid for prt images. */
    uint16_t prt_level_pitch[RADEON_SURF_MAX_LEVELS];
    /* Offset within slice in bytes, only valid for prt images. */
-   uint32_t prt_level_offset[RADEON_SURF_MAX_LEVELS];
+   uint64_t prt_level_offset[RADEON_SURF_MAX_LEVELS]; /* up to 64K * 64K * 16 * ~1.33 */
 
    /* DCC or HTILE level info */
-   struct gfx9_surf_level meta_levels[RADEON_SURF_MAX_LEVELS];
+   struct gfx9_surf_meta_level meta_levels[RADEON_SURF_MAX_LEVELS];
 
    union {
       /* Color */
@@ -288,7 +288,7 @@ struct gfx9_surf_layout {
          void *dcc_retile_map;
 
          /* CMASK level info (only level 0) */
-         struct gfx9_surf_level cmask_level0;
+         struct gfx9_surf_meta_level cmask_level0;
 
          /* For DCC retiling. */
          struct gfx9_meta_equation dcc_equation; /* 2D only */
@@ -334,9 +334,9 @@ struct radeon_surf {
     */
 
    /* Not supported yet for depth + stencil. */
-   uint16_t prt_tile_width;
-   uint16_t prt_tile_height;
-   uint16_t prt_tile_depth;
+   uint16_t prt_tile_width;   /* up to 256 roughly (for 64KB tiles) */
+   uint16_t prt_tile_height;  /* up to 256 roughly (for 64KB tiles) */
+   uint16_t prt_tile_depth;   /* up to 32 roughly (for 64KB thick tiles) */
 
    /* Tile swizzle can be OR'd with low bits of the BASE_256B address.
     * The value is the same for all mipmap levels. Supported tile modes: