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intel/isl: Don't over-allocate CLEAR_COLOR size to use whole cache line

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At the time this was added to fix some test failures. But it seems that
the failures were happening due to missing cache flushes, so
this extra space is no longer neccessary.

Fixes: 37b4eacc ("intel/isl: Resize clear color buffer to full cacheline")
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24768>
This commit is contained in:
Sviatoslav Peleshko 2023-08-18 00:46:00 +03:00 • committed by Marge Bot
parent 6d949e18fd
commit caa5c23e48
1 changed files with 1 additions and 2 deletions
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3
src/intel/isl/isl.c
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@ -307,8 +307,7 @@ isl_device_init(struct isl_device *dev,
dev->ss.size = RENDER_SURFACE_STATE_length(info) * 4;
dev->ss.align = isl_align(dev->ss.size, 32);
dev->ss.clear_color_state_size =
isl_align(CLEAR_COLOR_length(info) * 4, 64);
dev->ss.clear_color_state_size = CLEAR_COLOR_length(info) * 4;
dev->ss.clear_color_state_offset =
RENDER_SURFACE_STATE_ClearValueAddress_start(info) / 32 * 4;