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blorp: add missing pipecontrol after 3DSTATE_WM_HZ_OP for Xe2+

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Backport-to: 25.2
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37547>
This commit is contained in:
Tapani Pälli 2025-09-24 15:54:54 +03:00 • committed by Marge Bot
parent cc08786689
commit c8f47d7681
1 changed files with 14 additions and 0 deletions
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14
src/intel/blorp/blorp_genX_exec_brw.h
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@ -1587,6 +1587,20 @@ blorp_emit_gfx8_hiz_op(struct blorp_batch *batch,
blorp_emit(batch, GENX(3DSTATE_WM_HZ_OP), hzp);
#if GFX_VER >= 20
/* Xe2-3 Bspec 56469 (r52926):
*
* "8. 3DSTATE_WM_HZ_OP w/ none of the clear/resolve bits set
* followed by similar PC as 7 to commit this state."
*
* "7" refers to step 7 of the WM_HZ_OP command sequence.
*/
blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
pc.PostSyncOperation = WriteImmediateData;
pc.Address = blorp_get_workaround_address(batch);
}
#endif
blorp_measure_end(batch, params);
}