From c8f47d7681a5e8a5e346215150e3e333ce4d5ef5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tapani=20P=C3=A4lli?= <tapani.palli@intel.com>
Date: Wed, 24 Sep 2025 15:54:54 +0300
Subject: [PATCH] blorp: add missing pipecontrol after 3DSTATE_WM_HZ_OP for
 Xe2+
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Backport-to: 25.2
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37547>
---
 src/intel/blorp/blorp_genX_exec_brw.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/intel/blorp/blorp_genX_exec_brw.h b/src/intel/blorp/blorp_genX_exec_brw.h
index 9c930706582..de0d72ce576 100644
--- a/src/intel/blorp/blorp_genX_exec_brw.h
+++ b/src/intel/blorp/blorp_genX_exec_brw.h
@@ -1587,6 +1587,20 @@ blorp_emit_gfx8_hiz_op(struct blorp_batch *batch,
 
    blorp_emit(batch, GENX(3DSTATE_WM_HZ_OP), hzp);
 
+#if GFX_VER >= 20
+   /* Xe2-3 Bspec 56469 (r52926):
+    *
+    *  "8. 3DSTATE_WM_HZ_OP w/ none of the clear/resolve bits set
+    *  followed by similar PC as 7 to commit this state."
+    *
+    * "7" refers to step 7 of the WM_HZ_OP command sequence.
+    */
+   blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
+      pc.PostSyncOperation = WriteImmediateData;
+      pc.Address = blorp_get_workaround_address(batch);
+   }
+#endif
+
    blorp_measure_end(batch, params);
 }