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intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation

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Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815>
(cherry picked from commit 442628b702)
This commit is contained in:
Tapani Pälli 2022-01-31 11:48:49 +02:00 • committed by Dylan Baker
parent b8e9c345d0
commit c820bbced0
3 changed files with 3 additions and 1 deletions
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2
.pick_status.json
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@ -76,7 +76,7 @@
"description": "intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null
},

1
src/intel/genxml/gen12.xml
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@ -6450,6 +6450,7 @@
<instruction name="PIPE_CONTROL" bias="2" length="6" engine="render">
<field name="DWord Length" start="0" end="7" type="uint" default="4"/>
<field name="HDC Pipeline Flush Enable" start="9" end="9" type="bool"/>
<field name="L3 Read Only Cache Invalidation Enable" start="10" end="10" type="bool"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="0"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="2"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>

1
src/intel/genxml/gen125.xml
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@ -6781,6 +6781,7 @@
<instruction name="PIPE_CONTROL" bias="2" length="6" engine="render">
<field name="DWord Length" start="0" end="7" type="uint" default="4"/>
<field name="HDC Pipeline Flush Enable" start="9" end="9" type="bool"/>
<field name="L3 Read Only Cache Invalidation Enable" start="10" end="10" type="bool"/>
<field name="Untyped Data Port Cache Flush Enable" start="11" end="11" type="bool"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="0"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="2"/>