From c820bbced0bd852ae00e60506164a168e896d078 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tapani=20P=C3=A4lli?= Date: Mon, 31 Jan 2022 11:48:49 +0200 Subject: [PATCH] intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: mesa-stable Signed-off-by: Tapani Pälli Reviewed-by: Lionel Landwerlin Part-of: (cherry picked from commit 442628b70244f2c9fd0ed79e0656e999ee6fffca) --- .pick_status.json | 2 +- src/intel/genxml/gen12.xml | 1 + src/intel/genxml/gen125.xml | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/.pick_status.json b/.pick_status.json index d1817a7e0d5..0afd59ad3c5 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -76,7 +76,7 @@ "description": "intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null }, diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml index 08a49c33abf..c250da0c07c 100644 --- a/src/intel/genxml/gen12.xml +++ b/src/intel/genxml/gen12.xml @@ -6450,6 +6450,7 @@ + diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml index 6f2def17848..a11b70b405e 100644 --- a/src/intel/genxml/gen125.xml +++ b/src/intel/genxml/gen125.xml @@ -6781,6 +6781,7 @@ +