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intel/brw: Fix spill/fill count for load/store_scratch in SIMD32

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Honestly, I don't know what I was thinking - we are emitting a single
spill/fill message here, but were counting it as 2 spill/fills in SIMD32
shaders.  So our eventual shader stat reporting would subtract the
number of spills and fills from send_count, and get a negative number,
wrapping around to just shy of UINT32_MAX.  That's way too many sends.

This is especially noticable on Xe2 which often uses SIMD32 shaders.

Backport-to: 24.2
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31499>
This commit is contained in:
Kenneth Graunke 2024-10-02 02:32:26 -07:00 • committed by Marge Bot
parent 58d6906f8c
commit c747c1e1f4
1 changed files with 2 additions and 2 deletions
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4
src/intel/compiler/brw_fs_nir.cpp
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@ -7376,9 +7376,9 @@ fs_nir_emit_memory_access(nir_to_brw_state &ntb,
}
if (is_store)
s.shader_stats.spill_count += DIV_ROUND_UP(s.dispatch_width, 16);
++s.shader_stats.spill_count;
else
s.shader_stats.fill_count += DIV_ROUND_UP(s.dispatch_width, 16);
++s.shader_stats.fill_count;
data_src = 0;
break;