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pan/desc: Extend pan_emit_fbd() to support multilayer rendering
Right now, we always emit a framebuffer descriptor for the first layer in the RT views. Extend the logic so we can emit one FBD per layer we're supposed to render to without having to manually modify the RT views. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29450>
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parent
037eaa962b
commit
c694556657
4 changed files with 39 additions and 30 deletions
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@ -2538,7 +2538,7 @@ emit_fbd(struct panfrost_batch *batch, struct pan_fb_info *fb)
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#endif
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batch->framebuffer.gpu |=
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GENX(pan_emit_fbd)(fb, &tls, &batch->tiler_ctx, batch->framebuffer.cpu);
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GENX(pan_emit_fbd)(fb, 0, &tls, &batch->tiler_ctx, batch->framebuffer.cpu);
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}
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/* Mark a surface as written */
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@ -176,7 +176,8 @@ translate_s_format(enum pipe_format in)
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}
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static void
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pan_prepare_s(const struct pan_fb_info *fb, struct MALI_ZS_CRC_EXTENSION *ext)
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pan_prepare_s(const struct pan_fb_info *fb, unsigned layer_idx,
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struct MALI_ZS_CRC_EXTENSION *ext)
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{
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const struct pan_image_view *s = fb->zs.view.s;
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@ -189,7 +190,7 @@ pan_prepare_s(const struct pan_fb_info *fb, struct MALI_ZS_CRC_EXTENSION *ext)
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ext->s_msaa = mali_sampling_mode(s);
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struct pan_surface surf;
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pan_iview_get_surface(s, 0, 0, 0, &surf);
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pan_iview_get_surface(s, 0, layer_idx, 0, &surf);
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assert(image->layout.modifier ==
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DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED ||
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@ -205,7 +206,8 @@ pan_prepare_s(const struct pan_fb_info *fb, struct MALI_ZS_CRC_EXTENSION *ext)
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}
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static void
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pan_prepare_zs(const struct pan_fb_info *fb, struct MALI_ZS_CRC_EXTENSION *ext)
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pan_prepare_zs(const struct pan_fb_info *fb, unsigned layer_idx,
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struct MALI_ZS_CRC_EXTENSION *ext)
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{
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const struct pan_image_view *zs = fb->zs.view.zs;
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@ -218,7 +220,7 @@ pan_prepare_zs(const struct pan_fb_info *fb, struct MALI_ZS_CRC_EXTENSION *ext)
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ext->zs_msaa = mali_sampling_mode(zs);
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struct pan_surface surf;
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pan_iview_get_surface(zs, 0, 0, 0, &surf);
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pan_iview_get_surface(zs, 0, layer_idx, 0, &surf);
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UNUSED const struct pan_image_slice_layout *slice =
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&image->layout.slices[level];
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@ -295,13 +297,14 @@ pan_prepare_crc(const struct pan_fb_info *fb, int rt_crc,
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}
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static void
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pan_emit_zs_crc_ext(const struct pan_fb_info *fb, int rt_crc, void *zs_crc_ext)
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pan_emit_zs_crc_ext(const struct pan_fb_info *fb, unsigned layer_idx,
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int rt_crc, void *zs_crc_ext)
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{
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pan_pack(zs_crc_ext, ZS_CRC_EXTENSION, cfg) {
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pan_prepare_crc(fb, rt_crc, &cfg);
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cfg.zs_clean_pixel_write_enable = fb->zs.clear.z || fb->zs.clear.s;
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pan_prepare_zs(fb, &cfg);
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pan_prepare_s(fb, &cfg);
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pan_prepare_zs(fb, layer_idx, &cfg);
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pan_prepare_s(fb, layer_idx, &cfg);
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}
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}
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@ -433,21 +436,21 @@ pan_rt_init_format(const struct pan_image_view *rt,
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}
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static void
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pan_prepare_rt(const struct pan_fb_info *fb,
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unsigned idx, unsigned cbuf_offset,
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pan_prepare_rt(const struct pan_fb_info *fb, unsigned layer_idx,
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unsigned rt_idx, unsigned cbuf_offset,
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struct MALI_RENDER_TARGET *cfg)
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{
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cfg->clean_pixel_write_enable = fb->rts[idx].clear;
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cfg->clean_pixel_write_enable = fb->rts[rt_idx].clear;
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cfg->internal_buffer_offset = cbuf_offset;
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if (fb->rts[idx].clear) {
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cfg->clear.color_0 = fb->rts[idx].clear_value[0];
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cfg->clear.color_1 = fb->rts[idx].clear_value[1];
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cfg->clear.color_2 = fb->rts[idx].clear_value[2];
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cfg->clear.color_3 = fb->rts[idx].clear_value[3];
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if (fb->rts[rt_idx].clear) {
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cfg->clear.color_0 = fb->rts[rt_idx].clear_value[0];
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cfg->clear.color_1 = fb->rts[rt_idx].clear_value[1];
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cfg->clear.color_2 = fb->rts[rt_idx].clear_value[2];
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cfg->clear.color_3 = fb->rts[rt_idx].clear_value[3];
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}
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const struct pan_image_view *rt = fb->rts[idx].view;
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if (!rt || fb->rts[idx].discard) {
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const struct pan_image_view *rt = fb->rts[rt_idx].view;
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if (!rt || fb->rts[rt_idx].discard) {
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cfg->internal_format = MALI_COLOR_BUFFER_INTERNAL_FORMAT_R8G8B8A8;
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cfg->internal_buffer_offset = cbuf_offset;
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#if PAN_ARCH >= 7
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@ -463,8 +466,12 @@ pan_prepare_rt(const struct pan_fb_info *fb,
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cfg->dithering_enable = true;
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unsigned level = rt->first_level;
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ASSERTED unsigned layer_count = rt->dim == MALI_TEXTURE_DIMENSION_3D
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? rt->planes[0]->layout.depth
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: rt->last_layer - rt->first_layer + 1;
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assert(rt->last_level == rt->first_level);
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assert(rt->last_layer == rt->first_layer);
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assert(layer_idx < layer_count);
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int row_stride = image->layout.slices[level].row_stride;
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@ -481,7 +488,7 @@ pan_prepare_rt(const struct pan_fb_info *fb,
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cfg->writeback_block_format = mod_to_block_fmt(image->layout.modifier);
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struct pan_surface surf;
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pan_iview_get_surface(rt, 0, 0, 0, &surf);
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pan_iview_get_surface(rt, 0, layer_idx, 0, &surf);
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if (drm_is_afbc(image->layout.modifier)) {
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#if PAN_ARCH >= 9
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@ -601,11 +608,11 @@ pan_emit_midgard_tiler(const struct pan_fb_info *fb,
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#if PAN_ARCH >= 5
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static void
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pan_emit_rt(const struct pan_fb_info *fb,
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pan_emit_rt(const struct pan_fb_info *fb, unsigned layer_idx,
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unsigned idx, unsigned cbuf_offset, void *out)
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{
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pan_pack(out, RENDER_TARGET, cfg) {
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pan_prepare_rt(fb, idx, cbuf_offset, &cfg);
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pan_prepare_rt(fb, layer_idx, idx, cbuf_offset, &cfg);
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}
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}
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@ -674,7 +681,8 @@ pan_force_clean_write(const struct pan_fb_info *fb, unsigned tile_size)
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#endif
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unsigned
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GENX(pan_emit_fbd)(const struct pan_fb_info *fb, const struct pan_tls_info *tls,
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GENX(pan_emit_fbd)(const struct pan_fb_info *fb, unsigned layer_idx,
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const struct pan_tls_info *tls,
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const struct pan_tiler_context *tiler_ctx, void *out)
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{
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void *fbd = out;
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@ -791,14 +799,14 @@ GENX(pan_emit_fbd)(const struct pan_fb_info *fb, const struct pan_tls_info *tls,
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#endif
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if (has_zs_crc_ext) {
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pan_emit_zs_crc_ext(fb, crc_rt, out + pan_size(FRAMEBUFFER));
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pan_emit_zs_crc_ext(fb, layer_idx, crc_rt, out + pan_size(FRAMEBUFFER));
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rtd += pan_size(ZS_CRC_EXTENSION);
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}
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unsigned rt_count = MAX2(fb->rt_count, 1);
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unsigned cbuf_offset = 0;
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for (unsigned i = 0; i < rt_count; i++) {
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pan_emit_rt(fb, i, cbuf_offset, rtd);
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pan_emit_rt(fb, layer_idx, i, cbuf_offset, rtd);
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rtd += pan_size(RENDER_TARGET);
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if (!fb->rts[i].view)
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continue;
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@ -819,7 +827,8 @@ GENX(pan_emit_fbd)(const struct pan_fb_info *fb, const struct pan_tls_info *tls,
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}
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#else /* PAN_ARCH == 4 */
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unsigned
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GENX(pan_emit_fbd)(const struct pan_fb_info *fb, const struct pan_tls_info *tls,
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GENX(pan_emit_fbd)(const struct pan_fb_info *fb, unsigned layer_idx,
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const struct pan_tls_info *tls,
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const struct pan_tiler_context *tiler_ctx, void *fbd)
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{
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assert(fb->rt_count <= 1);
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@ -179,7 +179,7 @@ void GENX(pan_emit_tls)(const struct pan_tls_info *info, void *out);
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int GENX(pan_select_crc_rt)(const struct pan_fb_info *fb, unsigned tile_size);
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unsigned GENX(pan_emit_fbd)(const struct pan_fb_info *fb,
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unsigned GENX(pan_emit_fbd)(const struct pan_fb_info *fb, unsigned layer_idx,
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const struct pan_tls_info *tls,
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const struct pan_tiler_context *tiler_ctx,
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void *out);
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@ -150,9 +150,9 @@ panvk_per_arch(cmd_close_batch)(struct panvk_cmd_buffer *cmdbuf)
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panfrost_sample_positions_offset(
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pan_sample_pattern(fbinfo->nr_samples));
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batch->fb.desc.gpu |=
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GENX(pan_emit_fbd)(&cmdbuf->state.gfx.render.fb.info, &batch->tlsinfo,
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&batch->tiler.ctx, batch->fb.desc.cpu);
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batch->fb.desc.gpu |= GENX(pan_emit_fbd)(
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&cmdbuf->state.gfx.render.fb.info, 0, &batch->tlsinfo,
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&batch->tiler.ctx, batch->fb.desc.cpu);
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panvk_cmd_prepare_fragment_job(cmdbuf);
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}
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