From c6702e1530bd701a25f9ece608a294bd5d70a6b7 Mon Sep 17 00:00:00 2001 From: Yogesh Mohan Marimuthu Date: Tue, 18 Oct 2022 12:24:36 +0530 Subject: [PATCH] radv: fence complete struct is 4 qw size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit also libdrm function amdgpu_cs_chunk_fence_info_to_data() has qw multiplier and hence need not do it in radv_amdgpu_cs_submit(). Signed-off-by: Yogesh Mohan Marimuthu Reviewed-by: Marek Olšák Acked-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c index bf34206d0dc..5d4e661cab5 100644 --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c @@ -1531,7 +1531,7 @@ radv_amdgpu_ctx_create(struct radeon_winsys *_ws, enum radeon_ctx_priority prior } ctx->ws = ws; - assert(AMDGPU_HW_IP_NUM * MAX_RINGS_PER_TYPE * sizeof(uint64_t) <= 4096); + assert(AMDGPU_HW_IP_NUM * MAX_RINGS_PER_TYPE * 4 * sizeof(uint64_t) <= 4096); result = ws->base.buffer_create(&ws->base, 4096, 8, RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING, RADV_BO_PRIORITY_CS, 0, &ctx->fence_bo); @@ -1757,7 +1757,13 @@ radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx, struct radv_amdgpu_cs_request struct amdgpu_cs_fence_info fence_info; fence_info.handle = radv_amdgpu_winsys_bo(ctx->fence_bo)->bo; - fence_info.offset = (request->ip_type * MAX_RINGS_PER_TYPE + request->ring) * sizeof(uint64_t); + /* Need to reserve 4 QWORD for user fence: + * QWORD[0]: completed fence + * QWORD[1]: preempted fence + * QWORD[2]: reset fence + * QWORD[3]: preempted then reset + */ + fence_info.offset = (request->ip_type * MAX_RINGS_PER_TYPE + request->ring) * 4; amdgpu_cs_chunk_fence_info_to_data(&fence_info, &chunk_data[i]); }