fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-09 21:20:14 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

amd/vpelib: Refactor MPC registers

Browse source 
Refactor MPC registers.
3DLUT programming is largely the same but register are renamed to be in
VPMPC_RMCM (as opposed to VPMPCC_MCM). Note that they are still inside
MCM so governed by MCM control location.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Jack Chih <chiachih@amd.com>
Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30531>
This commit is contained in:
Kovac, Krunoslav 2024-04-26 10:38:09 -04:00 • committed by Marge Bot
parent 63d8fa3f28
commit c5e2c4feaf
5 changed files with 33 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

28
src/amd/vpelib/src/chip/vpe10/inc/vpe10_mpc.h
View file

@ -136,12 +136,11 @@ extern "C" {
SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_28_29, VPMPCC_MCM, id), \
SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_30_31, VPMPCC_MCM, id), \
SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_32_33, VPMPCC_MCM, id), \
SRIDFVL(VPMPCC_MCM_MEM_PWR_CTRL, VPMPCC_MCM, id)
SRIDFVL(VPMPCC_MCM_MEM_PWR_CTRL, VPMPCC_MCM, id)
#define MPC_REG_LIST_VPE10(id) \
MPC_REG_LIST_VPE10_COMMON(id), \
SRIDFVL(VPMPCC_MCM_SHAPER_CONTROL, VPMPCC_MCM, id), \
SRIDFVL(VPMPCC_MCM_SHAPER_CONTROL, VPMPCC_MCM, id), \
SRIDFVL(VPMPCC_MCM_SHAPER_OFFSET_R, VPMPCC_MCM, id), \
SRIDFVL(VPMPCC_MCM_SHAPER_OFFSET_G, VPMPCC_MCM, id), \
SRIDFVL(VPMPCC_MCM_SHAPER_OFFSET_B, VPMPCC_MCM, id), \
@ -908,7 +907,6 @@ extern "C" {
reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_28_29; \
reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_30_31; \
reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_32_33; \
reg_id_val VPMPCC_MCM_MEM_PWR_CTRL;
#define MPC_REG_VARIABLE_LIST_VPE10 \
MPC_REG_VARIABLE_LIST_VPE10_COMMON \
@ -952,7 +950,8 @@ extern "C" {
reg_id_val VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR; \
reg_id_val VPMPCC_MCM_3DLUT_OUT_OFFSET_R; \
reg_id_val VPMPCC_MCM_3DLUT_OUT_OFFSET_G; \
reg_id_val VPMPCC_MCM_3DLUT_OUT_OFFSET_B;
reg_id_val VPMPCC_MCM_3DLUT_OUT_OFFSET_B; \
reg_id_val VPMPCC_MCM_MEM_PWR_CTRL;
#define MPC_FIELD_VARIABLE_LIST_VPE10_COMMON(type) \
@ -1253,17 +1252,9 @@ extern "C" {
type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS; \
type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET; \
type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS; \
type VPMPCC_MCM_SHAPER_MEM_PWR_FORCE; \
type VPMPCC_MCM_SHAPER_MEM_PWR_DIS; \
type VPMPCC_MCM_SHAPER_MEM_LOW_PWR_MODE; \
type VPMPCC_MCM_3DLUT_MEM_PWR_FORCE; \
type VPMPCC_MCM_3DLUT_MEM_PWR_DIS; \
type VPMPCC_MCM_3DLUT_MEM_LOW_PWR_MODE; \
type VPMPCC_MCM_1DLUT_MEM_PWR_FORCE; \
type VPMPCC_MCM_1DLUT_MEM_PWR_DIS; \
type VPMPCC_MCM_1DLUT_MEM_LOW_PWR_MODE; \
type VPMPCC_MCM_SHAPER_MEM_PWR_STATE; \
type VPMPCC_MCM_3DLUT_MEM_PWR_STATE; \
type VPMPCC_MCM_1DLUT_MEM_PWR_STATE;
#define MPC_FIELD_VARIABLE_LIST_VPE10(type) \
@ -1379,7 +1370,16 @@ extern "C" {
type VPMPCC_MCM_3DLUT_OUT_OFFSET_G; \
type VPMPCC_MCM_3DLUT_OUT_SCALE_G; \
type VPMPCC_MCM_3DLUT_OUT_OFFSET_B; \
type VPMPCC_MCM_3DLUT_OUT_SCALE_B;
type VPMPCC_MCM_3DLUT_OUT_SCALE_B; \
type VPMPCC_MCM_SHAPER_MEM_PWR_STATE; \
type VPMPCC_MCM_3DLUT_MEM_PWR_STATE; \
type VPMPCC_MCM_SHAPER_MEM_PWR_FORCE; \
type VPMPCC_MCM_SHAPER_MEM_PWR_DIS; \
type VPMPCC_MCM_SHAPER_MEM_LOW_PWR_MODE; \
type VPMPCC_MCM_3DLUT_MEM_PWR_FORCE; \
type VPMPCC_MCM_3DLUT_MEM_PWR_DIS; \
type VPMPCC_MCM_3DLUT_MEM_LOW_PWR_MODE;
struct vpe10_mpc_registers {
MPC_REG_VARIABLE_LIST_VPE10

4
src/amd/vpelib/src/chip/vpe10/vpe10_resource.c
View file

@ -61,7 +61,7 @@
reg##reg_name##_##DEFAULT, false}
#define SRIDFVL1(reg_name) \
.reg_name = {BASE(reg##reg_name##_BASE_IDX) + reg##reg_name, reg##reg_name##_##DEFAULT, \
.reg_name = {BASE(reg##reg_name##_BASE_IDX) + reg##reg_name, reg##reg_name##_##DEFAULT, \
reg##reg_name##_##DEFAULT, false}
#define SRIDFVL2(reg_name, block, id) \
@ -69,7 +69,7 @@
reg##block##id##_##reg_name##_##DEFAULT, reg##block##id##_##reg_name##_##DEFAULT, false}
#define SRIDFVL3(reg_name, block, id) \
.block##_##reg_name = {BASE(reg##block##_##reg_name##_BASE_IDX) + reg##block##_##reg_name, \
.block##_##reg_name = {BASE(reg##block##_##reg_name##_BASE_IDX) + reg##block##_##reg_name, \
reg##block##_##reg_name##_##DEFAULT, reg##block##_##reg_name##_##DEFAULT, false}
/***************** CDC registers ****************/

1
src/amd/vpelib/src/core/inc/mpc.h
View file

@ -36,6 +36,7 @@ struct output_ctx;
enum mpc_mpccid {
MPC_MPCCID_0 = 0,
MPC_MPCCID_1 = 1,
MPC_MPCCID_COUNT,
};

14
src/amd/vpelib/src/utils/fixpt31_32.c
View file

@ -427,3 +427,17 @@ unsigned int vpe_to_fixed_point(
d_i = d_i & mask;
return d_i;
}
struct fixed31_32 vpe_fixpt_from_float(float f_val)
{
struct fixed31_32 res = vpe_fixpt_zero;
long long int_val = (long long) f_val;
float fractional = f_val - int_val;
long long frac_part =
(long long)(fractional * (1LL << FIXED31_32_BITS_PER_FRACTIONAL_PART));
res.value =
(int_val << FIXED31_32_BITS_PER_FRACTIONAL_PART) | (frac_part & FRACTIONAL_PART_MASK);
return res;
}

2
src/amd/vpelib/src/utils/inc/fixed31_32.h
View file

@ -543,6 +543,8 @@ static inline struct fixed31_32 vpe_fixpt_truncate(struct fixed31_32 arg, unsign
unsigned int vpe_to_fixed_point(
unsigned int decimalBits, double value, unsigned int mask, double d_pix);
struct fixed31_32 vpe_fixpt_from_float(float f_val);
#ifdef __cplusplus
}
#endif