diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_mpc.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_mpc.h index 3e76dbbcdf1..d0ac279e8e2 100644 --- a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_mpc.h +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_mpc.h @@ -136,12 +136,11 @@ extern "C" { SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_28_29, VPMPCC_MCM, id), \ SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_30_31, VPMPCC_MCM, id), \ SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_32_33, VPMPCC_MCM, id), \ - SRIDFVL(VPMPCC_MCM_MEM_PWR_CTRL, VPMPCC_MCM, id) - + SRIDFVL(VPMPCC_MCM_MEM_PWR_CTRL, VPMPCC_MCM, id) #define MPC_REG_LIST_VPE10(id) \ MPC_REG_LIST_VPE10_COMMON(id), \ - SRIDFVL(VPMPCC_MCM_SHAPER_CONTROL, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SHAPER_CONTROL, VPMPCC_MCM, id), \ SRIDFVL(VPMPCC_MCM_SHAPER_OFFSET_R, VPMPCC_MCM, id), \ SRIDFVL(VPMPCC_MCM_SHAPER_OFFSET_G, VPMPCC_MCM, id), \ SRIDFVL(VPMPCC_MCM_SHAPER_OFFSET_B, VPMPCC_MCM, id), \ @@ -908,7 +907,6 @@ extern "C" { reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_28_29; \ reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_30_31; \ reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_32_33; \ - reg_id_val VPMPCC_MCM_MEM_PWR_CTRL; #define MPC_REG_VARIABLE_LIST_VPE10 \ MPC_REG_VARIABLE_LIST_VPE10_COMMON \ @@ -952,7 +950,8 @@ extern "C" { reg_id_val VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR; \ reg_id_val VPMPCC_MCM_3DLUT_OUT_OFFSET_R; \ reg_id_val VPMPCC_MCM_3DLUT_OUT_OFFSET_G; \ - reg_id_val VPMPCC_MCM_3DLUT_OUT_OFFSET_B; + reg_id_val VPMPCC_MCM_3DLUT_OUT_OFFSET_B; \ + reg_id_val VPMPCC_MCM_MEM_PWR_CTRL; #define MPC_FIELD_VARIABLE_LIST_VPE10_COMMON(type) \ @@ -1253,17 +1252,9 @@ extern "C" { type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS; \ type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET; \ type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS; \ - type VPMPCC_MCM_SHAPER_MEM_PWR_FORCE; \ - type VPMPCC_MCM_SHAPER_MEM_PWR_DIS; \ - type VPMPCC_MCM_SHAPER_MEM_LOW_PWR_MODE; \ - type VPMPCC_MCM_3DLUT_MEM_PWR_FORCE; \ - type VPMPCC_MCM_3DLUT_MEM_PWR_DIS; \ - type VPMPCC_MCM_3DLUT_MEM_LOW_PWR_MODE; \ type VPMPCC_MCM_1DLUT_MEM_PWR_FORCE; \ type VPMPCC_MCM_1DLUT_MEM_PWR_DIS; \ type VPMPCC_MCM_1DLUT_MEM_LOW_PWR_MODE; \ - type VPMPCC_MCM_SHAPER_MEM_PWR_STATE; \ - type VPMPCC_MCM_3DLUT_MEM_PWR_STATE; \ type VPMPCC_MCM_1DLUT_MEM_PWR_STATE; #define MPC_FIELD_VARIABLE_LIST_VPE10(type) \ @@ -1379,7 +1370,16 @@ extern "C" { type VPMPCC_MCM_3DLUT_OUT_OFFSET_G; \ type VPMPCC_MCM_3DLUT_OUT_SCALE_G; \ type VPMPCC_MCM_3DLUT_OUT_OFFSET_B; \ - type VPMPCC_MCM_3DLUT_OUT_SCALE_B; + type VPMPCC_MCM_3DLUT_OUT_SCALE_B; \ + type VPMPCC_MCM_SHAPER_MEM_PWR_STATE; \ + type VPMPCC_MCM_3DLUT_MEM_PWR_STATE; \ + type VPMPCC_MCM_SHAPER_MEM_PWR_FORCE; \ + type VPMPCC_MCM_SHAPER_MEM_PWR_DIS; \ + type VPMPCC_MCM_SHAPER_MEM_LOW_PWR_MODE; \ + type VPMPCC_MCM_3DLUT_MEM_PWR_FORCE; \ + type VPMPCC_MCM_3DLUT_MEM_PWR_DIS; \ + type VPMPCC_MCM_3DLUT_MEM_LOW_PWR_MODE; + struct vpe10_mpc_registers { MPC_REG_VARIABLE_LIST_VPE10 diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c b/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c index 8cc3d68616d..1f5cdcb05c6 100644 --- a/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c @@ -61,7 +61,7 @@ reg##reg_name##_##DEFAULT, false} #define SRIDFVL1(reg_name) \ - .reg_name = {BASE(reg##reg_name##_BASE_IDX) + reg##reg_name, reg##reg_name##_##DEFAULT, \ + .reg_name = {BASE(reg##reg_name##_BASE_IDX) + reg##reg_name, reg##reg_name##_##DEFAULT, \ reg##reg_name##_##DEFAULT, false} #define SRIDFVL2(reg_name, block, id) \ @@ -69,7 +69,7 @@ reg##block##id##_##reg_name##_##DEFAULT, reg##block##id##_##reg_name##_##DEFAULT, false} #define SRIDFVL3(reg_name, block, id) \ - .block##_##reg_name = {BASE(reg##block##_##reg_name##_BASE_IDX) + reg##block##_##reg_name, \ + .block##_##reg_name = {BASE(reg##block##_##reg_name##_BASE_IDX) + reg##block##_##reg_name, \ reg##block##_##reg_name##_##DEFAULT, reg##block##_##reg_name##_##DEFAULT, false} /***************** CDC registers ****************/ diff --git a/src/amd/vpelib/src/core/inc/mpc.h b/src/amd/vpelib/src/core/inc/mpc.h index 3a4162cbbf1..8e7406b54b2 100644 --- a/src/amd/vpelib/src/core/inc/mpc.h +++ b/src/amd/vpelib/src/core/inc/mpc.h @@ -36,6 +36,7 @@ struct output_ctx; enum mpc_mpccid { MPC_MPCCID_0 = 0, + MPC_MPCCID_1 = 1, MPC_MPCCID_COUNT, }; diff --git a/src/amd/vpelib/src/utils/fixpt31_32.c b/src/amd/vpelib/src/utils/fixpt31_32.c index 18dca6041ae..7e501afdece 100644 --- a/src/amd/vpelib/src/utils/fixpt31_32.c +++ b/src/amd/vpelib/src/utils/fixpt31_32.c @@ -427,3 +427,17 @@ unsigned int vpe_to_fixed_point( d_i = d_i & mask; return d_i; } + +struct fixed31_32 vpe_fixpt_from_float(float f_val) +{ + struct fixed31_32 res = vpe_fixpt_zero; + long long int_val = (long long) f_val; + float fractional = f_val - int_val; + long long frac_part = + (long long)(fractional * (1LL << FIXED31_32_BITS_PER_FRACTIONAL_PART)); + + res.value = + (int_val << FIXED31_32_BITS_PER_FRACTIONAL_PART) | (frac_part & FRACTIONAL_PART_MASK); + + return res; +} diff --git a/src/amd/vpelib/src/utils/inc/fixed31_32.h b/src/amd/vpelib/src/utils/inc/fixed31_32.h index 694b4993132..eb05493cedf 100644 --- a/src/amd/vpelib/src/utils/inc/fixed31_32.h +++ b/src/amd/vpelib/src/utils/inc/fixed31_32.h @@ -543,6 +543,8 @@ static inline struct fixed31_32 vpe_fixpt_truncate(struct fixed31_32 arg, unsign unsigned int vpe_to_fixed_point( unsigned int decimalBits, double value, unsigned int mask, double d_pix); +struct fixed31_32 vpe_fixpt_from_float(float f_val); + #ifdef __cplusplus } #endif