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brw: Drop dead code from dispatch limit check for dual source blending

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We checked that ver is 11 or 12.  It can't be >= 20.  This is dead code.

Dual source blending on Xe2 does not have native SIMD32 RT write message
support, but SIMD splitting is currently lowering it to low/high SIMD16
message pairs when using SIMD32 dispatch.  I'm not aware of any of the
hardware errata from previous platform still applying.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41122>
This commit is contained in:
Kenneth Graunke 2026-03-09 12:02:06 -07:00 • committed by Marge Bot
parent 599d26db00
commit c5928d40ae
1 changed files with 2 additions and 6 deletions
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8
src/intel/compiler/brw/brw_compile_fs.cpp
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@ -166,12 +166,8 @@ brw_emit_fb_writes(brw_shader &s)
* dispatch on ICL due some unknown reasons, see
* https://gitlab.freedesktop.org/mesa/mesa/-/issues/2183
*/
if (devinfo->ver >= 20)
s.limit_dispatch_width(16, "Dual source blending unsupported "
"in SIMD32 mode.\n");
else
s.limit_dispatch_width(8, "Dual source blending unsupported "
"in SIMD16 and SIMD32 modes.\n");
s.limit_dispatch_width(8, "Dual source blending unsupported "
"in SIMD16 and SIMD32 modes.\n");
}
brw_do_emit_fb_writes(s, key->nr_color_regions, replicate_alpha);