From c5928d40ae9a9b4460d7c672863531017e39a256 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Mon, 9 Mar 2026 12:02:06 -0700 Subject: [PATCH] brw: Drop dead code from dispatch limit check for dual source blending We checked that ver is 11 or 12. It can't be >= 20. This is dead code. Dual source blending on Xe2 does not have native SIMD32 RT write message support, but SIMD splitting is currently lowering it to low/high SIMD16 message pairs when using SIMD32 dispatch. I'm not aware of any of the hardware errata from previous platform still applying. Reviewed-by: Alyssa Rosenzweig Part-of: --- src/intel/compiler/brw/brw_compile_fs.cpp | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/src/intel/compiler/brw/brw_compile_fs.cpp b/src/intel/compiler/brw/brw_compile_fs.cpp index 7517db28b2a..eb20c253831 100644 --- a/src/intel/compiler/brw/brw_compile_fs.cpp +++ b/src/intel/compiler/brw/brw_compile_fs.cpp @@ -166,12 +166,8 @@ brw_emit_fb_writes(brw_shader &s) * dispatch on ICL due some unknown reasons, see * https://gitlab.freedesktop.org/mesa/mesa/-/issues/2183 */ - if (devinfo->ver >= 20) - s.limit_dispatch_width(16, "Dual source blending unsupported " - "in SIMD32 mode.\n"); - else - s.limit_dispatch_width(8, "Dual source blending unsupported " - "in SIMD16 and SIMD32 modes.\n"); + s.limit_dispatch_width(8, "Dual source blending unsupported " + "in SIMD16 and SIMD32 modes.\n"); } brw_do_emit_fb_writes(s, key->nr_color_regions, replicate_alpha);