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gallium/radeon: remove radeon_info::r600_tiling_config

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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Marek Olšák 2016-01-30 02:54:47 +01:00
parent 4f96846d9d
commit c577f2843a
4 changed files with 9 additions and 24 deletions
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1
src/gallium/drivers/radeon/r600_pipe_common.c
View file

@ -899,7 +899,6 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config);
printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);

1
src/gallium/drivers/radeon/radeon_winsys.h
View file

@ -278,7 +278,6 @@ struct radeon_info {
uint32_t r600_gb_backend_map; /* R600 harvest config */
boolean r600_gb_backend_map_valid;
uint32_t r600_num_banks;
uint32_t r600_tiling_config;
uint32_t num_render_backends;
uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */
uint32_t pipe_interleave_bytes;

15
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
View file

@ -92,20 +92,6 @@ static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
}
}
/* Convert Sea Islands register values GB_ADDR_CFG and MC_ADDR_CFG
* into GB_TILING_CONFIG register which is only present on R600-R700. */
static unsigned r600_get_gb_tiling_config(struct amdgpu_gpu_info *info)
{
unsigned num_pipes = info->gb_addr_cfg & 0x7;
unsigned num_banks = info->mc_arb_ramcfg & 0x3;
unsigned pipe_interleave_bytes = (info->gb_addr_cfg >> 4) & 0x7;
unsigned row_size = (info->gb_addr_cfg >> 28) & 0x3;
return num_pipes | (num_banks << 4) |
(pipe_interleave_bytes << 8) |
(row_size << 12);
}
/* Helper function to do the ioctls needed for setup and init. */
static boolean do_winsys_init(struct amdgpu_winsys *ws)
{
@ -263,7 +249,6 @@ static boolean do_winsys_init(struct amdgpu_winsys *ws)
ws->info.has_userptr = TRUE;
ws->info.num_render_backends = ws->amdinfo.rb_pipes;
ws->info.clock_crystal_freq = ws->amdinfo.gpu_counter_freq;
ws->info.r600_tiling_config = r600_get_gb_tiling_config(&ws->amdinfo);
ws->info.num_tile_pipes = cik_get_num_tile_pipes(&ws->amdinfo);
ws->info.pipe_interleave_bytes = 256 << ((ws->amdinfo.gb_addr_cfg >> 4) & 0x7);
ws->info.has_virtual_memory = TRUE;

16
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
View file

@ -372,6 +372,8 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
return FALSE;
}
else if (ws->gen >= DRV_R600) {
uint32_t tiling_config = 0;
if (ws->info.drm_minor >= 9 &&
!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
"num backends",
@ -383,17 +385,17 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
&ws->info.clock_crystal_freq);
radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
&ws->info.r600_tiling_config);
&tiling_config);
ws->info.r600_num_banks =
ws->info.chip_class >= EVERGREEN ?
4 << ((ws->info.r600_tiling_config & 0xf0) >> 4) :
4 << ((ws->info.r600_tiling_config & 0x30) >> 4);
4 << ((tiling_config & 0xf0) >> 4) :
4 << ((tiling_config & 0x30) >> 4);
ws->info.pipe_interleave_bytes =
ws->info.chip_class >= EVERGREEN ?
256 << ((ws->info.r600_tiling_config & 0xf00) >> 8) :
256 << ((ws->info.r600_tiling_config & 0xc0) >> 6);
256 << ((tiling_config & 0xf00) >> 8) :
256 << ((tiling_config & 0xc0) >> 6);
if (!ws->info.pipe_interleave_bytes)
ws->info.pipe_interleave_bytes =
@ -409,8 +411,8 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
} else {
ws->info.num_tile_pipes =
ws->info.chip_class >= EVERGREEN ?
1 << (ws->info.r600_tiling_config & 0xf) :
1 << ((ws->info.r600_tiling_config & 0xe) >> 1);
1 << (tiling_config & 0xf) :
1 << ((tiling_config & 0xe) >> 1);
}
ws->info.has_virtual_memory = FALSE;