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gallium/radeon: get pipe_interleave_bytes AKA group_bytes from the winsys

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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Marek Olšák 2016-01-30 02:50:34 +01:00
parent 276621da45
commit 4f96846d9d
7 changed files with 16 additions and 65 deletions
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2
src/gallium/drivers/r600/evergreen_state.c
View file

@ -986,7 +986,7 @@ void evergreen_init_color_surface_rat(struct r600_context *rctx,
unsigned block_size =
align(util_format_get_blocksize(pipe_buffer->format), 4);
unsigned pitch_alignment =
MAX2(64, rctx->screen->b.tiling_info.group_bytes / block_size);
MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
/* XXX: This is copied from evergreen_init_color_surface(). I don't

57
src/gallium/drivers/radeon/r600_pipe_common.c
View file

@ -800,59 +800,6 @@ static boolean r600_fence_finish(struct pipe_screen *screen,
return rws->fence_wait(rws, rfence->gfx, timeout);
}
static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
uint32_t tiling_config)
{
switch ((tiling_config & 0xc0) >> 6) {
case 0:
rscreen->tiling_info.group_bytes = 256;
break;
case 1:
rscreen->tiling_info.group_bytes = 512;
break;
default:
return false;
}
return true;
}
static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
uint32_t tiling_config)
{
switch ((tiling_config & 0xf00) >> 8) {
case 0:
rscreen->tiling_info.group_bytes = 256;
break;
case 1:
rscreen->tiling_info.group_bytes = 512;
break;
default:
return false;
}
return true;
}
static bool r600_init_tiling(struct r600_common_screen *rscreen)
{
uint32_t tiling_config = rscreen->info.r600_tiling_config;
/* set default group bytes, overridden by tiling info ioctl */
if (rscreen->chip_class <= R700) {
rscreen->tiling_info.group_bytes = 256;
} else {
rscreen->tiling_info.group_bytes = 512;
}
if (!tiling_config)
return true;
if (rscreen->chip_class <= R700) {
return r600_interpret_tiling(rscreen, tiling_config);
} else {
return evergreen_interpret_tiling(rscreen, tiling_config);
}
}
struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
const struct pipe_resource *templ)
{
@ -909,9 +856,6 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
rscreen->chip_class = rscreen->info.chip_class;
rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
if (!r600_init_tiling(rscreen)) {
return false;
}
util_format_s3tc_init();
pipe_mutex_init(rscreen->aux_context_lock);
pipe_mutex_init(rscreen->gpu_load_mutex);
@ -959,6 +903,7 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
}

5
src/gallium/drivers/radeon/r600_pipe_common.h
View file

@ -281,17 +281,12 @@ struct r600_surface {
unsigned pa_su_poly_offset_db_fmt_cntl;
};
struct r600_tiling_info {
unsigned group_bytes;
};
struct r600_common_screen {
struct pipe_screen b;
struct radeon_winsys *ws;
enum radeon_family family;
enum chip_class chip_class;
struct radeon_info info;
struct r600_tiling_info tiling_info;
uint64_t debug_flags;
bool has_cp_dma;
bool has_streamout;

6
src/gallium/drivers/radeon/r600_texture.c
View file

@ -362,7 +362,7 @@ void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
unsigned element_bits = 4;
unsigned cmask_cache_bits = 1024;
unsigned num_pipes = rscreen->info.num_tile_pipes;
unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
@ -394,7 +394,7 @@ static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
struct r600_texture *rtex,
struct r600_cmask_info *out)
{
unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
unsigned num_pipes = rscreen->info.num_tile_pipes;
unsigned cl_width, cl_height;
@ -569,7 +569,7 @@ static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
slice_elements = (width * height) / (8 * 8);
slice_bytes = slice_elements * 4;
pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
base_align = num_pipes * pipe_interleave_bytes;
rtex->htile.pitch = width;

1
src/gallium/drivers/radeon/radeon_winsys.h
View file

@ -281,6 +281,7 @@ struct radeon_info {
uint32_t r600_tiling_config;
uint32_t num_render_backends;
uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */
uint32_t pipe_interleave_bytes;
uint32_t enabled_rb_mask; /* GCN harvest config */
/* Tile modes. */

1
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
View file

@ -265,6 +265,7 @@ static boolean do_winsys_init(struct amdgpu_winsys *ws)
ws->info.clock_crystal_freq = ws->amdinfo.gpu_counter_freq;
ws->info.r600_tiling_config = r600_get_gb_tiling_config(&ws->amdinfo);
ws->info.num_tile_pipes = cik_get_num_tile_pipes(&ws->amdinfo);
ws->info.pipe_interleave_bytes = 256 << ((ws->amdinfo.gb_addr_cfg >> 4) & 0x7);
ws->info.has_virtual_memory = TRUE;
ws->info.has_sdma = dma.available_rings != 0;

9
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
View file

@ -390,6 +390,15 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
4 << ((ws->info.r600_tiling_config & 0xf0) >> 4) :
4 << ((ws->info.r600_tiling_config & 0x30) >> 4);
ws->info.pipe_interleave_bytes =
ws->info.chip_class >= EVERGREEN ?
256 << ((ws->info.r600_tiling_config & 0xf00) >> 8) :
256 << ((ws->info.r600_tiling_config & 0xc0) >> 6);
if (!ws->info.pipe_interleave_bytes)
ws->info.pipe_interleave_bytes =
ws->info.chip_class >= EVERGREEN ? 512 : 256;
if (ws->info.drm_minor >= 11) {
radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
&ws->info.num_tile_pipes);