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i965: Re-order depth/stencil/hiz/clear packets to match ISL

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Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jason Ekstrand 2018-05-05 12:35:01 -07:00
parent 6fc3404911
commit c4d00da7b7
3 changed files with 56 additions and 56 deletions
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42
src/mesa/drivers/dri/i965/gen6_depth_state.c
View file

@ -155,27 +155,6 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
* failure to do so causes hangs on gen5 and a stall on gen6.
*/
/* Emit hiz buffer. */
if (hiz) {
assert(depth_mt);
uint32_t offset;
isl_surf_get_image_offset_B_tile_sa(&depth_mt->aux_buf->surf,
lod, 0, 0, &offset, NULL, NULL);
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH(depth_mt->aux_buf->surf.row_pitch - 1);
OUT_RELOC(depth_mt->aux_buf->bo, RELOC_WRITE, offset);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
}
/* Emit stencil buffer. */
if (separate_stencil) {
assert(stencil_mt->format == MESA_FORMAT_S_UINT8);
@ -197,6 +176,27 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH(0);
ADVANCE_BATCH();
}
/* Emit hiz buffer. */
if (hiz) {
assert(depth_mt);
uint32_t offset;
isl_surf_get_image_offset_B_tile_sa(&depth_mt->aux_buf->surf,
lod, 0, 0, &offset, NULL, NULL);
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH(depth_mt->aux_buf->surf.row_pitch - 1);
OUT_RELOC(depth_mt->aux_buf->bo, RELOC_WRITE, offset);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
}
}
/*

34
src/mesa/drivers/dri/i965/gen7_misc_state.c
View file

@ -137,23 +137,6 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH((depth - 1) << 21);
ADVANCE_BATCH();
if (!hiz) {
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
assert(depth_mt);
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
OUT_BATCH((mocs << 25) |
(depth_mt->aux_buf->pitch - 1));
OUT_RELOC(depth_mt->aux_buf->bo, RELOC_WRITE, 0);
ADVANCE_BATCH();
}
if (stencil_mt == NULL) {
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
@ -173,6 +156,23 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
ADVANCE_BATCH();
}
if (!hiz) {
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
assert(depth_mt);
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
OUT_BATCH((mocs << 25) |
(depth_mt->aux_buf->pitch - 1));
OUT_RELOC(depth_mt->aux_buf->bo, RELOC_WRITE, 0);
ADVANCE_BATCH();
}
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
if (depth_mt) {

36
src/mesa/drivers/dri/i965/gen8_depth_state.c
View file

@ -82,24 +82,6 @@ emit_depth_packets(struct brw_context *brw,
(depth_mt ? depth_mt->surf.array_pitch_el_rows >> 2 : 0));
ADVANCE_BATCH();
if (!hiz) {
BEGIN_BATCH(5);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
assert(depth_mt);
BEGIN_BATCH(5);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
OUT_BATCH((depth_mt->aux_buf->pitch - 1) | mocs_wb << 25);
OUT_RELOC64(depth_mt->aux_buf->bo, RELOC_WRITE, 0);
OUT_BATCH(depth_mt->aux_buf->qpitch >> 2);
ADVANCE_BATCH();
}
if (stencil_mt == NULL) {
BEGIN_BATCH(5);
OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
@ -118,6 +100,24 @@ emit_depth_packets(struct brw_context *brw,
ADVANCE_BATCH();
}
if (!hiz) {
BEGIN_BATCH(5);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
assert(depth_mt);
BEGIN_BATCH(5);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
OUT_BATCH((depth_mt->aux_buf->pitch - 1) | mocs_wb << 25);
OUT_RELOC64(depth_mt->aux_buf->bo, RELOC_WRITE, 0);
OUT_BATCH(depth_mt->aux_buf->qpitch >> 2);
ADVANCE_BATCH();
}
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
OUT_BATCH(depth_mt ? depth_mt->fast_clear_color.u32[0] : 0);