From c4d00da7b7b819e21d07e00cdb9b14f670c8e262 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Sat, 5 May 2018 12:35:01 -0700 Subject: [PATCH] i965: Re-order depth/stencil/hiz/clear packets to match ISL Reviewed-by: Topi Pohjolainen Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/gen6_depth_state.c | 42 ++++++++++---------- src/mesa/drivers/dri/i965/gen7_misc_state.c | 34 ++++++++-------- src/mesa/drivers/dri/i965/gen8_depth_state.c | 36 ++++++++--------- 3 files changed, 56 insertions(+), 56 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c index 8a1d5808051..bca956e23d2 100644 --- a/src/mesa/drivers/dri/i965/gen6_depth_state.c +++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c @@ -155,27 +155,6 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw, * failure to do so causes hangs on gen5 and a stall on gen6. */ - /* Emit hiz buffer. */ - if (hiz) { - assert(depth_mt); - - uint32_t offset; - isl_surf_get_image_offset_B_tile_sa(&depth_mt->aux_buf->surf, - lod, 0, 0, &offset, NULL, NULL); - - BEGIN_BATCH(3); - OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); - OUT_BATCH(depth_mt->aux_buf->surf.row_pitch - 1); - OUT_RELOC(depth_mt->aux_buf->bo, RELOC_WRITE, offset); - ADVANCE_BATCH(); - } else { - BEGIN_BATCH(3); - OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); - OUT_BATCH(0); - OUT_BATCH(0); - ADVANCE_BATCH(); - } - /* Emit stencil buffer. */ if (separate_stencil) { assert(stencil_mt->format == MESA_FORMAT_S_UINT8); @@ -197,6 +176,27 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw, OUT_BATCH(0); ADVANCE_BATCH(); } + + /* Emit hiz buffer. */ + if (hiz) { + assert(depth_mt); + + uint32_t offset; + isl_surf_get_image_offset_B_tile_sa(&depth_mt->aux_buf->surf, + lod, 0, 0, &offset, NULL, NULL); + + BEGIN_BATCH(3); + OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); + OUT_BATCH(depth_mt->aux_buf->surf.row_pitch - 1); + OUT_RELOC(depth_mt->aux_buf->bo, RELOC_WRITE, offset); + ADVANCE_BATCH(); + } else { + BEGIN_BATCH(3); + OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + } } /* diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c index 15084733c5c..e3a355fae38 100644 --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c @@ -137,23 +137,6 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw, OUT_BATCH((depth - 1) << 21); ADVANCE_BATCH(); - if (!hiz) { - BEGIN_BATCH(3); - OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2)); - OUT_BATCH(0); - OUT_BATCH(0); - ADVANCE_BATCH(); - } else { - assert(depth_mt); - - BEGIN_BATCH(3); - OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2)); - OUT_BATCH((mocs << 25) | - (depth_mt->aux_buf->pitch - 1)); - OUT_RELOC(depth_mt->aux_buf->bo, RELOC_WRITE, 0); - ADVANCE_BATCH(); - } - if (stencil_mt == NULL) { BEGIN_BATCH(3); OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2)); @@ -173,6 +156,23 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw, ADVANCE_BATCH(); } + if (!hiz) { + BEGIN_BATCH(3); + OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + } else { + assert(depth_mt); + + BEGIN_BATCH(3); + OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2)); + OUT_BATCH((mocs << 25) | + (depth_mt->aux_buf->pitch - 1)); + OUT_RELOC(depth_mt->aux_buf->bo, RELOC_WRITE, 0); + ADVANCE_BATCH(); + } + BEGIN_BATCH(3); OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2)); if (depth_mt) { diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c index 0fc027313b4..1c77218d2bc 100644 --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c @@ -82,24 +82,6 @@ emit_depth_packets(struct brw_context *brw, (depth_mt ? depth_mt->surf.array_pitch_el_rows >> 2 : 0)); ADVANCE_BATCH(); - if (!hiz) { - BEGIN_BATCH(5); - OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2)); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - ADVANCE_BATCH(); - } else { - assert(depth_mt); - BEGIN_BATCH(5); - OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2)); - OUT_BATCH((depth_mt->aux_buf->pitch - 1) | mocs_wb << 25); - OUT_RELOC64(depth_mt->aux_buf->bo, RELOC_WRITE, 0); - OUT_BATCH(depth_mt->aux_buf->qpitch >> 2); - ADVANCE_BATCH(); - } - if (stencil_mt == NULL) { BEGIN_BATCH(5); OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2)); @@ -118,6 +100,24 @@ emit_depth_packets(struct brw_context *brw, ADVANCE_BATCH(); } + if (!hiz) { + BEGIN_BATCH(5); + OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + } else { + assert(depth_mt); + BEGIN_BATCH(5); + OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2)); + OUT_BATCH((depth_mt->aux_buf->pitch - 1) | mocs_wb << 25); + OUT_RELOC64(depth_mt->aux_buf->bo, RELOC_WRITE, 0); + OUT_BATCH(depth_mt->aux_buf->qpitch >> 2); + ADVANCE_BATCH(); + } + BEGIN_BATCH(3); OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2)); OUT_BATCH(depth_mt ? depth_mt->fast_clear_color.u32[0] : 0);