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radeonsi: Better indexing of parameters in the pixel shader.

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We were previously using the TGSI input index, which can exceed the number of
parameters passed from the vertex shader via the parameter cache. Now we use
a separate index which only counts those parameters.

Prevents piglit regressions with the following fix.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Michel Dänzer 2012-09-27 20:01:33 +02:00 • committed by Michel Dänzer
parent dbb4a7f950
commit c3db19efba
3 changed files with 12 additions and 8 deletions
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10
src/gallium/drivers/radeonsi/radeonsi_shader.c
View file

@ -236,6 +236,7 @@ static void declare_input_fs(
{ {
const char * intr_name; const char * intr_name;
unsigned chan; unsigned chan;
struct si_shader *shader = &si_shader_ctx->shader->shader;
struct lp_build_context * base = struct lp_build_context * base =
&si_shader_ctx->radeon_bld.soa.bld_base.base; &si_shader_ctx->radeon_bld.soa.bld_base.base;
struct gallivm_state * gallivm = base->gallivm; struct gallivm_state * gallivm = base->gallivm;
@ -249,10 +250,7 @@ static void declare_input_fs(
* *
*/ */
LLVMValueRef params = use_sgpr(base->gallivm, SGPR_I32, SI_PS_NUM_USER_SGPR); LLVMValueRef params = use_sgpr(base->gallivm, SGPR_I32, SI_PS_NUM_USER_SGPR);
LLVMValueRef attr_number;
/* XXX: Is this the input_index? */
LLVMValueRef attr_number = lp_build_const_int32(gallivm, input_index);
if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) { if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) { for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
@ -268,6 +266,10 @@ static void declare_input_fs(
return; return;
} }
shader->input[input_index].param_offset = shader->ninterp++;
attr_number = lp_build_const_int32(gallivm,
shader->input[input_index].param_offset);
/* XXX: Handle all possible interpolation modes */ /* XXX: Handle all possible interpolation modes */
switch (decl->Interp.Interpolate) { switch (decl->Interp.Interpolate) {
case TGSI_INTERPOLATE_COLOR: case TGSI_INTERPOLATE_COLOR:

1
src/gallium/drivers/radeonsi/radeonsi_shader.h
View file

@ -71,6 +71,7 @@ struct si_shader {
unsigned noutput; unsigned noutput;
struct si_shader_io output[32]; struct si_shader_io output[32];
unsigned ninterp;
bool uses_kill; bool uses_kill;
bool fs_write_all; bool fs_write_all;
unsigned nr_cbufs; unsigned nr_cbufs;

9
src/gallium/drivers/radeonsi/si_state_draw.c
View file

@ -101,7 +101,6 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s
struct si_pm4_state *pm4; struct si_pm4_state *pm4;
unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control; unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
unsigned num_sgprs, num_user_sgprs; unsigned num_sgprs, num_user_sgprs;
int ninterp = 0;
boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE; boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
unsigned fragcoord_interp_mode = 0; unsigned fragcoord_interp_mode = 0;
unsigned spi_baryc_cntl, spi_ps_input_ena; unsigned spi_baryc_cntl, spi_ps_input_ena;
@ -131,7 +130,7 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s
} }
continue; continue;
} }
ninterp++;
/* XXX: Flat shading hangs the GPU */ /* XXX: Flat shading hangs the GPU */
if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_CONSTANT || if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
(shader->shader.input[i].interpolate == TGSI_INTERPOLATE_COLOR && (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
@ -172,7 +171,7 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s
exports_ps = 2; exports_ps = 2;
} }
spi_ps_in_control = S_0286D8_NUM_INTERP(ninterp); spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.ninterp);
spi_baryc_cntl = 0; spi_baryc_cntl = 0;
if (have_perspective) if (have_perspective)
@ -365,7 +364,9 @@ static void si_update_spi_map(struct r600_context *rctx)
tmp |= S_028644_OFFSET(0x20); tmp |= S_028644_OFFSET(0x20);
} }
si_pm4_set_reg(pm4, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp); si_pm4_set_reg(pm4,
R_028644_SPI_PS_INPUT_CNTL_0 + ps->input[i].param_offset * 4,
tmp);
} }
si_pm4_set_state(rctx, spi, pm4); si_pm4_set_state(rctx, spi, pm4);