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nouveau: Delete the NV50_PROG_USE_TGSI env var.

Browse source 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23114>
This commit is contained in:
Emma Anholt 2023-05-18 13:05:17 -07:00 • committed by Marge Bot
parent ae777b1836
commit c3cbe610df
13 changed files with 43 additions and 123 deletions
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1
src/gallium/drivers/nouveau/nouveau_debug.h
View file

@ -7,7 +7,6 @@
#include "util/u_debug.h" #include "util/u_debug.h"
#define NOUVEAU_DEBUG_MISC 0x0001 #define NOUVEAU_DEBUG_MISC 0x0001
#define NOUVEAU_DEBUG_USE_TGSI 0x0002
#define NOUVEAU_DEBUG_SHADER 0x0100 #define NOUVEAU_DEBUG_SHADER 0x0100
#define NOUVEAU_DEBUG_PROG_IR 0x0200 #define NOUVEAU_DEBUG_PROG_IR 0x0200
#define NOUVEAU_DEBUG_PROG_RA 0x0400 #define NOUVEAU_DEBUG_PROG_RA 0x0400

5
src/gallium/drivers/nouveau/nouveau_screen.c
View file

@ -170,10 +170,7 @@ nouveau_disk_cache_create(struct nouveau_screen *screen)
_mesa_sha1_final(&ctx, sha1); _mesa_sha1_final(&ctx, sha1);
mesa_bytes_to_hex(cache_id, sha1, 20); mesa_bytes_to_hex(cache_id, sha1, 20);
if (screen->prefer_nir)
driver_flags |= NOUVEAU_SHADER_CACHE_FLAGS_IR_NIR; driver_flags |= NOUVEAU_SHADER_CACHE_FLAGS_IR_NIR;
else
driver_flags |= NOUVEAU_SHADER_CACHE_FLAGS_IR_TGSI;
screen->disk_shader_cache = screen->disk_shader_cache =
disk_cache_create(nouveau_screen_get_name(&screen->base), disk_cache_create(nouveau_screen_get_name(&screen->base),
@ -283,8 +280,6 @@ nouveau_screen_init(struct nouveau_screen *screen, struct nouveau_device *dev)
if (nv_dbg) if (nv_dbg)
nouveau_mesa_debug = atoi(nv_dbg); nouveau_mesa_debug = atoi(nv_dbg);
screen->prefer_nir = !debug_get_bool_option("NV50_PROG_USE_TGSI", false);
screen->force_enable_cl = debug_get_bool_option("NOUVEAU_ENABLE_CL", false); screen->force_enable_cl = debug_get_bool_option("NOUVEAU_ENABLE_CL", false);
if (screen->force_enable_cl) if (screen->force_enable_cl)
glsl_type_singleton_init_or_ref(); glsl_type_singleton_init_or_ref();

1
src/gallium/drivers/nouveau/nouveau_screen.h
View file

@ -65,7 +65,6 @@ struct nouveau_screen {
struct disk_cache *disk_shader_cache; struct disk_cache *disk_shader_cache;
bool prefer_nir;
bool force_enable_cl; bool force_enable_cl;
bool has_svm; bool has_svm;
bool is_uma; bool is_uma;

4
src/gallium/drivers/nouveau/nv30/nv30_screen.c
View file

@ -345,7 +345,7 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_TEMPS: case PIPE_SHADER_CAP_MAX_TEMPS:
return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13; return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
case PIPE_SHADER_CAP_PREFERRED_IR: case PIPE_SHADER_CAP_PREFERRED_IR:
return (NOUVEAU_DEBUG & NOUVEAU_DEBUG_USE_TGSI) ? PIPE_SHADER_IR_TGSI : PIPE_SHADER_IR_NIR; return PIPE_SHADER_IR_NIR;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return 0; return 0;
@ -400,7 +400,7 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return 16; return 16;
case PIPE_SHADER_CAP_PREFERRED_IR: case PIPE_SHADER_CAP_PREFERRED_IR:
return (NOUVEAU_DEBUG & NOUVEAU_DEBUG_USE_TGSI) ? PIPE_SHADER_IR_TGSI : PIPE_SHADER_IR_NIR; return PIPE_SHADER_IR_NIR;
case PIPE_SHADER_CAP_CONT_SUPPORTED: case PIPE_SHADER_CAP_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:

17
src/gallium/drivers/nouveau/nv50/nv50_screen.c
View file

@ -255,11 +255,10 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return 1; return 1;
case PIPE_CAP_ALPHA_TEST: case PIPE_CAP_ALPHA_TEST:
/* nvc0 has fixed function alpha test support, but nv50 doesn't. The TGSI /* nvc0 has fixed function alpha test support, but nv50 doesn't. If we
* backend emits the conditional discard code against a driver-uploaded * don't have it, then the frontend will lower it for us.
* uniform, but with NIR we can have the st emit it for us.
*/ */
return class_3d >= NVC0_3D_CLASS || !screen->prefer_nir; return class_3d >= NVC0_3D_CLASS;
case PIPE_CAP_TEXTURE_TRANSFER_MODES: case PIPE_CAP_TEXTURE_TRANSFER_MODES:
return PIPE_TEXTURE_TRANSFER_BLIT; return PIPE_TEXTURE_TRANSFER_BLIT;
@ -316,8 +315,6 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
enum pipe_shader_type shader, enum pipe_shader_type shader,
enum pipe_shader_cap param) enum pipe_shader_cap param)
{ {
const struct nouveau_screen *screen = nouveau_screen(pscreen);
switch (shader) { switch (shader) {
case PIPE_SHADER_VERTEX: case PIPE_SHADER_VERTEX:
case PIPE_SHADER_GEOMETRY: case PIPE_SHADER_GEOMETRY:
@ -377,12 +374,9 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
return shader == PIPE_SHADER_COMPUTE ? NV50_MAX_GLOBALS - 1 : 0; return shader == PIPE_SHADER_COMPUTE ? NV50_MAX_GLOBALS - 1 : 0;
case PIPE_SHADER_CAP_PREFERRED_IR: case PIPE_SHADER_CAP_PREFERRED_IR:
return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI; return PIPE_SHADER_IR_NIR;
case PIPE_SHADER_CAP_SUPPORTED_IRS: case PIPE_SHADER_CAP_SUPPORTED_IRS:
if (screen->prefer_nir)
return 1 << PIPE_SHADER_IR_NIR; return 1 << PIPE_SHADER_IR_NIR;
else
return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR);
case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
@ -854,9 +848,8 @@ nv50_screen_get_compiler_options(struct pipe_screen *pscreen,
enum pipe_shader_ir ir, enum pipe_shader_ir ir,
enum pipe_shader_type shader) enum pipe_shader_type shader)
{ {
struct nouveau_screen *screen = nouveau_screen(pscreen);
if (ir == PIPE_SHADER_IR_NIR) if (ir == PIPE_SHADER_IR_NIR)
return nv50_ir_nir_shader_compiler_options(NVISA_G80_CHIPSET, shader, screen->prefer_nir); return nv50_ir_nir_shader_compiler_options(NVISA_G80_CHIPSET, shader);
return NULL; return NULL;
} }

10
src/gallium/drivers/nouveau/nv50/nv50_state.c
View file

@ -741,7 +741,6 @@ nv50_sp_state_create(struct pipe_context *pipe,
enum pipe_shader_type type) enum pipe_shader_type type)
{ {
struct nv50_program *prog; struct nv50_program *prog;
const struct nouveau_screen *screen = nouveau_screen(pipe->screen);
prog = CALLOC_STRUCT(nv50_program); prog = CALLOC_STRUCT(nv50_program);
if (!prog) if (!prog)
@ -752,12 +751,8 @@ nv50_sp_state_create(struct pipe_context *pipe,
switch (cso->type) { switch (cso->type) {
case PIPE_SHADER_IR_TGSI: case PIPE_SHADER_IR_TGSI:
if (screen->prefer_nir) {
prog->pipe.type = PIPE_SHADER_IR_NIR; prog->pipe.type = PIPE_SHADER_IR_NIR;
prog->pipe.ir.nir = tgsi_to_nir(cso->tokens, pipe->screen, false); prog->pipe.ir.nir = tgsi_to_nir(cso->tokens, pipe->screen, false);
} else {
prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
}
break; break;
case PIPE_SHADER_IR_NIR: case PIPE_SHADER_IR_NIR:
prog->pipe.ir.nir = cso->ir.nir; prog->pipe.ir.nir = cso->ir.nir;
@ -848,7 +843,6 @@ nv50_cp_state_create(struct pipe_context *pipe,
const struct pipe_compute_state *cso) const struct pipe_compute_state *cso)
{ {
struct nv50_program *prog; struct nv50_program *prog;
const struct nouveau_screen *screen = nouveau_screen(pipe->screen);
prog = CALLOC_STRUCT(nv50_program); prog = CALLOC_STRUCT(nv50_program);
if (!prog) if (!prog)
@ -859,12 +853,8 @@ nv50_cp_state_create(struct pipe_context *pipe,
switch(cso->ir_type) { switch(cso->ir_type) {
case PIPE_SHADER_IR_TGSI: { case PIPE_SHADER_IR_TGSI: {
const struct tgsi_token *tokens = cso->prog; const struct tgsi_token *tokens = cso->prog;
if (screen->prefer_nir) {
prog->pipe.type = PIPE_SHADER_IR_NIR; prog->pipe.type = PIPE_SHADER_IR_NIR;
prog->pipe.ir.nir = tgsi_to_nir(tokens, pipe->screen, false); prog->pipe.ir.nir = tgsi_to_nir(tokens, pipe->screen, false);
} else {
prog->pipe.tokens = tgsi_dup_tokens(tokens);
}
break; break;
} }
case PIPE_SHADER_IR_NIR: case PIPE_SHADER_IR_NIR:

3
src/gallium/drivers/nouveau/nv50/nv50_surface.c
View file

@ -938,8 +938,7 @@ nv50_blitter_make_fp(struct pipe_context *pipe,
const int chipset = nouveau_screen(pipe->screen)->device->chipset; const int chipset = nouveau_screen(pipe->screen)->device->chipset;
const nir_shader_compiler_options *options = const nir_shader_compiler_options *options =
nv50_ir_nir_shader_compiler_options(chipset, PIPE_SHADER_FRAGMENT, nv50_ir_nir_shader_compiler_options(chipset, PIPE_SHADER_FRAGMENT);
true);
struct nir_builder b = struct nir_builder b =
nir_builder_init_simple_shader(MESA_SHADER_FRAGMENT, options, nir_builder_init_simple_shader(MESA_SHADER_FRAGMENT, options,

2
src/gallium/drivers/nouveau/nvc0/nvc0_program.c
View file

@ -1016,7 +1016,7 @@ nvc0_program_init_tcp_empty(struct nvc0_context *nvc0)
{ {
const nir_shader_compiler_options *options = const nir_shader_compiler_options *options =
nv50_ir_nir_shader_compiler_options(nvc0->screen->base.device->chipset, nv50_ir_nir_shader_compiler_options(nvc0->screen->base.device->chipset,
PIPE_SHADER_TESS_CTRL, true); PIPE_SHADER_TESS_CTRL);
struct nir_builder b = struct nir_builder b =
nir_builder_init_simple_shader(MESA_SHADER_TESS_CTRL, options, nir_builder_init_simple_shader(MESA_SHADER_TESS_CTRL, options,

10
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
View file

@ -329,11 +329,10 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_SYSTEM_SVM: case PIPE_CAP_SYSTEM_SVM:
return screen->has_svm ? 1 : 0; return screen->has_svm ? 1 : 0;
/* caps has to be turned on with nir */
case PIPE_CAP_GL_SPIRV: case PIPE_CAP_GL_SPIRV:
case PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS: case PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS:
case PIPE_CAP_INT64_DIVMOD: case PIPE_CAP_INT64_DIVMOD:
return screen->prefer_nir ? 1 : 0; return 1;
/* nir related caps */ /* nir related caps */
case PIPE_CAP_NIR_IMAGES_AS_DEREF: case PIPE_CAP_NIR_IMAGES_AS_DEREF:
@ -397,11 +396,9 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
switch (param) { switch (param) {
case PIPE_SHADER_CAP_PREFERRED_IR: case PIPE_SHADER_CAP_PREFERRED_IR:
return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI; return PIPE_SHADER_IR_NIR;
case PIPE_SHADER_CAP_SUPPORTED_IRS: { case PIPE_SHADER_CAP_SUPPORTED_IRS: {
uint32_t irs = 1 << PIPE_SHADER_IR_NIR; uint32_t irs = 1 << PIPE_SHADER_IR_NIR;
if (!screen->prefer_nir && class_3d < GV100_3D_CLASS)
irs |= 1 << PIPE_SHADER_IR_TGSI;
if (screen->force_enable_cl) if (screen->force_enable_cl)
irs |= 1 << PIPE_SHADER_IR_NIR_SERIALIZED; irs |= 1 << PIPE_SHADER_IR_NIR_SERIALIZED;
return irs; return irs;
@ -946,8 +943,7 @@ nvc0_screen_get_compiler_options(struct pipe_screen *pscreen,
{ {
struct nvc0_screen *screen = nvc0_screen(pscreen); struct nvc0_screen *screen = nvc0_screen(pscreen);
if (ir == PIPE_SHADER_IR_NIR) if (ir == PIPE_SHADER_IR_NIR)
return nv50_ir_nir_shader_compiler_options(screen->base.device->chipset, return nv50_ir_nir_shader_compiler_options(screen->base.device->chipset, shader);
shader, screen->base.prefer_nir);
return NULL; return NULL;
} }

10
src/gallium/drivers/nouveau/nvc0/nvc0_state.c
View file

@ -601,7 +601,6 @@ nvc0_sp_state_create(struct pipe_context *pipe,
const struct pipe_shader_state *cso, unsigned type) const struct pipe_shader_state *cso, unsigned type)
{ {
struct nvc0_program *prog; struct nvc0_program *prog;
const struct nouveau_screen *screen = nouveau_screen(pipe->screen);
prog = CALLOC_STRUCT(nvc0_program); prog = CALLOC_STRUCT(nvc0_program);
if (!prog) if (!prog)
@ -612,12 +611,8 @@ nvc0_sp_state_create(struct pipe_context *pipe,
switch(cso->type) { switch(cso->type) {
case PIPE_SHADER_IR_TGSI: case PIPE_SHADER_IR_TGSI:
if (screen->prefer_nir) {
prog->pipe.type = PIPE_SHADER_IR_NIR; prog->pipe.type = PIPE_SHADER_IR_NIR;
prog->pipe.ir.nir = tgsi_to_nir(cso->tokens, pipe->screen, false); prog->pipe.ir.nir = tgsi_to_nir(cso->tokens, pipe->screen, false);
} else {
prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
}
break; break;
case PIPE_SHADER_IR_NIR: case PIPE_SHADER_IR_NIR:
prog->pipe.ir.nir = cso->ir.nir; prog->pipe.ir.nir = cso->ir.nir;
@ -741,7 +736,6 @@ nvc0_cp_state_create(struct pipe_context *pipe,
const struct pipe_compute_state *cso) const struct pipe_compute_state *cso)
{ {
struct nvc0_program *prog; struct nvc0_program *prog;
const struct nouveau_screen *screen = nouveau_screen(pipe->screen);
prog = CALLOC_STRUCT(nvc0_program); prog = CALLOC_STRUCT(nvc0_program);
if (!prog) if (!prog)
@ -755,12 +749,8 @@ nvc0_cp_state_create(struct pipe_context *pipe,
switch(cso->ir_type) { switch(cso->ir_type) {
case PIPE_SHADER_IR_TGSI: { case PIPE_SHADER_IR_TGSI: {
const struct tgsi_token *tokens = cso->prog; const struct tgsi_token *tokens = cso->prog;
if (screen->prefer_nir) {
prog->pipe.type = PIPE_SHADER_IR_NIR; prog->pipe.type = PIPE_SHADER_IR_NIR;
prog->pipe.ir.nir = tgsi_to_nir(tokens, pipe->screen, false); prog->pipe.ir.nir = tgsi_to_nir(tokens, pipe->screen, false);
} else {
prog->pipe.tokens = tgsi_dup_tokens(tokens);
}
break; break;
} }
case PIPE_SHADER_IR_NIR: case PIPE_SHADER_IR_NIR:

2
src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
View file

@ -854,7 +854,7 @@ nvc0_blitter_make_vp(struct pipe_context *pipe)
{ {
const nir_shader_compiler_options *options = const nir_shader_compiler_options *options =
nv50_ir_nir_shader_compiler_options(nouveau_screen(pipe->screen)->device->chipset, nv50_ir_nir_shader_compiler_options(nouveau_screen(pipe->screen)->device->chipset,
PIPE_SHADER_VERTEX, true); PIPE_SHADER_VERTEX);
struct nir_builder b = struct nir_builder b =
nir_builder_init_simple_shader(MESA_SHADER_VERTEX, options, nir_builder_init_simple_shader(MESA_SHADER_VERTEX, options,

2
src/nouveau/codegen/nv50_ir_driver.h
View file

@ -220,7 +220,7 @@ extern "C" {
#endif #endif
const struct nir_shader_compiler_options * const struct nir_shader_compiler_options *
nv50_ir_nir_shader_compiler_options(int chipset, uint8_t shader_type, bool prefer_nir); nv50_ir_nir_shader_compiler_options(int chipset, uint8_t shader_type);
extern int nv50_ir_generate_code(struct nv50_ir_prog_info *, extern int nv50_ir_generate_code(struct nv50_ir_prog_info *,
struct nv50_ir_prog_info_out *); struct nv50_ir_prog_info_out *);

63
src/nouveau/codegen/nv50_ir_from_nir.cpp
View file

@ -3304,7 +3304,7 @@ Program::makeFromNIR(struct nv50_ir_prog_info *info,
} // namespace nv50_ir } // namespace nv50_ir
static nir_shader_compiler_options static nir_shader_compiler_options
nvir_nir_shader_compiler_options(int chipset, uint8_t shader_type, bool prefer_nir) nvir_nir_shader_compiler_options(int chipset, uint8_t shader_type)
{ {
nir_shader_compiler_options op = {}; nir_shader_compiler_options op = {};
op.lower_fdiv = (chipset >= NVISA_GV100_CHIPSET); op.lower_fdiv = (chipset >= NVISA_GV100_CHIPSET);
@ -3385,7 +3385,7 @@ nvir_nir_shader_compiler_options(int chipset, uint8_t shader_type, bool prefer_n
op.lower_mul_2x32_64 = true; // TODO op.lower_mul_2x32_64 = true; // TODO
op.lower_rotate = (chipset < NVISA_GV100_CHIPSET); op.lower_rotate = (chipset < NVISA_GV100_CHIPSET);
op.has_imul24 = false; op.has_imul24 = false;
op.has_fmulz = (prefer_nir && (chipset > NVISA_G80_CHIPSET)); op.has_fmulz = (chipset > NVISA_G80_CHIPSET);
op.intel_vec4 = false; op.intel_vec4 = false;
op.lower_uniforms_to_ubo = true; op.lower_uniforms_to_ubo = true;
op.force_indirect_unrolling = (nir_variable_mode) ( op.force_indirect_unrolling = (nir_variable_mode) (
@ -3429,93 +3429,52 @@ nvir_nir_shader_compiler_options(int chipset, uint8_t shader_type, bool prefer_n
} }
static const nir_shader_compiler_options g80_nir_shader_compiler_options = static const nir_shader_compiler_options g80_nir_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_G80_CHIPSET, PIPE_SHADER_TYPES, true); nvir_nir_shader_compiler_options(NVISA_G80_CHIPSET, PIPE_SHADER_TYPES);
static const nir_shader_compiler_options g80_fs_nir_shader_compiler_options = static const nir_shader_compiler_options g80_fs_nir_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_G80_CHIPSET, PIPE_SHADER_FRAGMENT, true); nvir_nir_shader_compiler_options(NVISA_G80_CHIPSET, PIPE_SHADER_FRAGMENT);
static const nir_shader_compiler_options gf100_nir_shader_compiler_options = static const nir_shader_compiler_options gf100_nir_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET, PIPE_SHADER_TYPES, true); nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET, PIPE_SHADER_TYPES);
static const nir_shader_compiler_options gf100_fs_nir_shader_compiler_options = static const nir_shader_compiler_options gf100_fs_nir_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET, PIPE_SHADER_FRAGMENT, true); nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET, PIPE_SHADER_FRAGMENT);
static const nir_shader_compiler_options gm107_nir_shader_compiler_options = static const nir_shader_compiler_options gm107_nir_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET, PIPE_SHADER_TYPES, true); nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET, PIPE_SHADER_TYPES);
static const nir_shader_compiler_options gm107_fs_nir_shader_compiler_options = static const nir_shader_compiler_options gm107_fs_nir_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET, PIPE_SHADER_FRAGMENT, true); nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET, PIPE_SHADER_FRAGMENT);
static const nir_shader_compiler_options gv100_nir_shader_compiler_options = static const nir_shader_compiler_options gv100_nir_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET, PIPE_SHADER_TYPES, true); nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET, PIPE_SHADER_TYPES);
static const nir_shader_compiler_options gv100_fs_nir_shader_compiler_options = static const nir_shader_compiler_options gv100_fs_nir_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET, PIPE_SHADER_FRAGMENT, true); nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET, PIPE_SHADER_FRAGMENT);
static const nir_shader_compiler_options g80_tgsi_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_G80_CHIPSET, PIPE_SHADER_TYPES, false);
static const nir_shader_compiler_options g80_fs_tgsi_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_G80_CHIPSET, PIPE_SHADER_FRAGMENT, false);
static const nir_shader_compiler_options gf100_tgsi_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET, PIPE_SHADER_TYPES, false);
static const nir_shader_compiler_options gf100_fs_tgsi_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET, PIPE_SHADER_FRAGMENT, false);
static const nir_shader_compiler_options gm107_tgsi_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET, PIPE_SHADER_TYPES, false);
static const nir_shader_compiler_options gm107_fs_tgsi_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET, PIPE_SHADER_FRAGMENT, false);
static const nir_shader_compiler_options gv100_tgsi_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET, PIPE_SHADER_TYPES, false);
static const nir_shader_compiler_options gv100_fs_tgsi_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET, PIPE_SHADER_FRAGMENT, false);
const nir_shader_compiler_options * const nir_shader_compiler_options *
nv50_ir_nir_shader_compiler_options(int chipset, uint8_t shader_type, bool prefer_nir) nv50_ir_nir_shader_compiler_options(int chipset, uint8_t shader_type)
{ {
if (chipset >= NVISA_GV100_CHIPSET) { if (chipset >= NVISA_GV100_CHIPSET) {
if (shader_type == PIPE_SHADER_FRAGMENT) { if (shader_type == PIPE_SHADER_FRAGMENT) {
if (prefer_nir)
return &gv100_fs_nir_shader_compiler_options; return &gv100_fs_nir_shader_compiler_options;
else
return &gv100_fs_tgsi_shader_compiler_options;
} else { } else {
if (prefer_nir)
return &gv100_nir_shader_compiler_options; return &gv100_nir_shader_compiler_options;
else
return &gv100_tgsi_shader_compiler_options;
} }
} }
if (chipset >= NVISA_GM107_CHIPSET) { if (chipset >= NVISA_GM107_CHIPSET) {
if (shader_type == PIPE_SHADER_FRAGMENT) { if (shader_type == PIPE_SHADER_FRAGMENT) {
if (prefer_nir)
return &gm107_fs_nir_shader_compiler_options; return &gm107_fs_nir_shader_compiler_options;
else
return &gm107_fs_tgsi_shader_compiler_options;
} else { } else {
if (prefer_nir)
return &gm107_nir_shader_compiler_options; return &gm107_nir_shader_compiler_options;
else
return &gm107_tgsi_shader_compiler_options;
} }
} }
if (chipset >= NVISA_GF100_CHIPSET) { if (chipset >= NVISA_GF100_CHIPSET) {
if (shader_type == PIPE_SHADER_FRAGMENT) { if (shader_type == PIPE_SHADER_FRAGMENT) {
if (prefer_nir)
return &gf100_fs_nir_shader_compiler_options; return &gf100_fs_nir_shader_compiler_options;
else
return &gf100_fs_tgsi_shader_compiler_options;
} else { } else {
if (prefer_nir)
return &gf100_nir_shader_compiler_options; return &gf100_nir_shader_compiler_options;
else
return &gf100_tgsi_shader_compiler_options;
} }
} }
if (shader_type == PIPE_SHADER_FRAGMENT) { if (shader_type == PIPE_SHADER_FRAGMENT) {
if (prefer_nir)
return &g80_fs_nir_shader_compiler_options; return &g80_fs_nir_shader_compiler_options;
else
return &g80_fs_tgsi_shader_compiler_options;
} else { } else {
if (prefer_nir)
return &g80_nir_shader_compiler_options; return &g80_nir_shader_compiler_options;
else
return &g80_tgsi_shader_compiler_options;
} }
} }