r300: Drop RADEON_DEBUG=use_tgsi.

The NIR path is default, and well-trodden at this point.  By dropping
support for input as TGSI, we get rely on the NIR trig lowering.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23114>
This commit is contained in:
Emma Anholt 2023-05-18 13:20:12 -07:00 committed by Marge Bot
parent 715dcf4053
commit ae777b1836
9 changed files with 1 additions and 50 deletions

View file

@ -1615,8 +1615,6 @@ r300 driver environment variables
Disable hierarchical zbuffer
``nocmask``
Disable AA compression and fast AA clear
``use_tgsi``
Request TGSI shaders from the state tracker
``notcl``
Disable hardware accelerated Transform/Clip/Lighting

View file

@ -85,7 +85,6 @@ void r3xx_compile_fragment_program(struct r300_fragment_program_compiler* c)
struct radeon_program_transformation native_rewrite_r500[] = {
{ &radeonTransformALU, NULL },
{ &radeonTransformDeriv, NULL },
{ &radeonTransformTrigScale, NULL },
{ NULL, NULL }
};

View file

@ -56,7 +56,6 @@ struct radeon_compiler {
unsigned has_presub:1;
unsigned has_omod:1;
unsigned disable_optimizations:1;
unsigned needs_trig_input_transform:1;
unsigned max_temp_regs;
unsigned max_constants;
int max_alu_insts;

View file

@ -1036,43 +1036,6 @@ static void r300_transform_SIN_COS(struct radeon_compiler *c,
rc_remove_instruction(inst);
}
/**
* Transform the trigonometric functions COS and SIN
* to include pre-scaling by 1/(2*PI) and taking the fractional
* part, so that the input to COS and SIN is always in the range [0,1).
*
* @warning This transformation implicitly changes the semantics of SIN and COS!
*/
int radeonTransformTrigScale(struct radeon_compiler* c,
struct rc_instruction* inst,
void* unused)
{
static const float RCP_2PI = 0.15915494309189535;
unsigned int temp;
unsigned int constant;
unsigned int constant_swizzle;
if (inst->U.I.Opcode != RC_OPCODE_COS &&
inst->U.I.Opcode != RC_OPCODE_SIN)
return 0;
if (!c->needs_trig_input_transform)
return 1;
temp = rc_find_free_temporary(c);
constant = rc_constants_add_immediate_scalar(&c->Program.Constants, RCP_2PI, &constant_swizzle);
emit2(c, inst->Prev, RC_OPCODE_MUL, NULL, dstregtmpmask(temp, RC_MASK_W),
swizzle_xxxx(inst->U.I.SrcReg[0]),
srcregswz(RC_FILE_CONSTANT, constant, constant_swizzle));
emit1(c, inst->Prev, RC_OPCODE_FRC, NULL, dstregtmpmask(temp, RC_MASK_W),
srcreg(RC_FILE_TEMPORARY, temp));
r300_transform_SIN_COS(c, inst, temp);
return 1;
}
/**
* Replaces DDX/DDY instructions with MOV 0 to avoid using dummy shaders on r300/r400.
*

View file

@ -45,11 +45,6 @@ int r300_transform_trig_simple(
struct rc_instruction * inst,
void*);
int radeonTransformTrigScale(
struct radeon_compiler * c,
struct rc_instruction * inst,
void*);
int r300_transform_trig_scale_vertex(
struct radeon_compiler *c,
struct rc_instruction *inst,

View file

@ -50,7 +50,6 @@ static const struct debug_named_value r300_debug_options[] = {
{ "nozmask", DBG_NO_ZMASK, "Disable zbuffer compression" },
{ "nohiz", DBG_NO_HIZ, "Disable hierarchical zbuffer" },
{ "nocmask", DBG_NO_CMASK, "Disable AA compression and fast AA clear" },
{ "use_tgsi", DBG_USE_TGSI, "Request TGSI shaders from the state tracker" },
{ "notcl", DBG_NO_TCL, "Disable hardware accelerated Transform/Clip/Lighting" },
/* must be last */

View file

@ -456,7 +456,6 @@ static void r300_translate_fragment_shader(
compiler.Base.has_half_swizzles = TRUE;
compiler.Base.has_presub = TRUE;
compiler.Base.has_omod = TRUE;
compiler.Base.needs_trig_input_transform = DBG_ON(r300, DBG_USE_TGSI);
compiler.Base.max_temp_regs =
compiler.Base.is_r500 ? 128 : (compiler.Base.is_r400 ? 64 : 32);
compiler.Base.max_constants = compiler.Base.is_r500 ? 256 : 32;

View file

@ -256,7 +256,7 @@ static int r300_get_shader_param(struct pipe_screen *pscreen,
switch (param) {
case PIPE_SHADER_CAP_PREFERRED_IR:
return (r300screen->debug & DBG_USE_TGSI) ? PIPE_SHADER_IR_TGSI : PIPE_SHADER_IR_NIR;
return PIPE_SHADER_IR_NIR;
case PIPE_SHADER_CAP_SUPPORTED_IRS:
return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
default:

View file

@ -103,7 +103,6 @@ radeon_winsys(struct pipe_screen *screen) {
#define DBG_NO_ZMASK (1 << 21)
#define DBG_NO_HIZ (1 << 22)
#define DBG_NO_CMASK (1 << 23)
#define DBG_USE_TGSI (1 << 24)
#define DBG_NO_TCL (1 << 25)
/*@}*/
static inline boolean SCREEN_DBG_ON(struct r300_screen * screen, unsigned flags)